US4942522A
Expired / Lapsed
US
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Timer channel with multiple timer reference features
Assignee: NXP USA Inc
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Filing: 1988-08-19
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Granted: 1990-07-17
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Expires: 2008-08-19
Abstract
Abstract A timer channel with multiple timer reference signals available to it which is capable of performing any input or output timer function with reference to any of the available reference signals. In addition, input timer functions may be related to the occurrence of output functions. For instance, the state of one timer reference may be captured automatically at a specified time referenced to another timer reference. Another feature of the invention provides for the creation of a time-out window for an input timer function through the use of a concurrent output function.
Inventors
- 👤 Brian F. Wilkie
- 👤 Vernon B. Goler
- 👤 Stanley E. Groves
- 👤 John J. Vaglica
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 09:33
CPC Classifications
G; G06; G06F; G06F1/00; G06F1/04; G06F1/14; G04; G04G; G04G3/00
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
145 words
A timer responsive to at least two timer reference signals comprising: a capture register; a match register; first timer reference select means for selecting one of said at least two timer reference signals; second timer reference select means for selecting one of said at least two timer reference signals; capture logic means responsive to an input to the timer to load said capture register with a representation of a value of the timer reference signal selected by said first timer reference select means; and match logic means responsive to the contents of said match register and to the value of the timer reference signal selected by said second timer reference select means to produce a match output if a predetermined relationship exists between the value of the timer reference signal selected by said second timer reference select means and the contents of the match register.
Claim 2
Dependent Claim
145 words
A timer responsive to at least two timer reference signals comprising: a capture register; a match register; first timer reference select means for selecting one of said at least two timer reference signals; second timer reference select means for selecting one of said at least two timer reference signals; capture logic means responsive to an input to the timer to load said capture register with a representation of a value of the timer reference signal selected by said first timer reference select means; and match logic means responsive to the contents of said match register and to the value of the timer reference signal selected by said second timer reference select means to produce a match output if a predetermined relationship exists between the value of the timer reference signal selected by said second timer reference select means and the contents of the match register.
Claim 3
Dependent Claim
47 words
A timer according to claim 1 wherein: said capture logic means is further responsive to said match output of said match logic means to load said capture register with a representation of a value of the timer reference signal selected by said first timer reference select means.
Claim 4
Dependent Claim
41 words
A timer according to claim 1 further comprising: service request logic means for producing a first service request signal in response to said input to the timer and for producing a second service request signal in response to said match output.
Claim 5
Dependent Claim
30 words
A timer system comprising: a plurality of timers according to claim 1; and means for supplying said at least two timer reference signals to each of said plurality of timers.
Claim 6
Dependent Claim
156 words
A timer system comprising means for generating at least two timer reference signals and a timer channel, the timer channel further comprising: a capture register; a match register; first timer reference select means for selecting one of said at least two timer reference signals; second timer reference select means for selecting one of said at least two timer reference signals; capture logic means responsive to an input to the timer to load said capture register with a representation of a value of the timer reference signal selected by said first timer reference select means; and match logic means responsive to the contents of said match register and to the value of the timer reference signal selected by said second timer reference select means to produce a match output if a predetermined relationship exists between the value of the timer reference signal selected by said second timer reference select means and the contents of the match register.
Claim 7
Dependent Claim
156 words
A timer system comprising means for generating at least two timer reference signals and a timer channel, the timer channel further comprising: a capture register; a match register; first timer reference select means for selecting one of said at least two timer reference signals; second timer reference select means for selecting one of said at least two timer reference signals; capture logic means responsive to an input to the timer to load said capture register with a representation of a value of the timer reference signal selected by said first timer reference select means; and match logic means responsive to the contents of said match register and to the value of the timer reference signal selected by said second timer reference select means to produce a match output if a predetermined relationship exists between the value of the timer reference signal selected by said second timer reference select means and the contents of the match register.
Claim 8
Dependent Claim
47 words
A timer according to claim 5 wherein: said capture logic means is further responsive to said match output of said match logic means to load said capture register with a representation of a value of the timer reference signal selected by said first timer reference select means.
Claim 9
Dependent Claim
41 words
A timer according to claim 6 further comprising: service request logic means for producing a first service request signal in response to said input to the timer and for producing a second service request signal in response to said match output.
Claim 10
Dependent Claim
55 words
A timer according to claim 7 further comprising: a pin; and pin control logic means coupled to said capture logic means and said match logic means for one of detecting an event occurring at said pin and triggering said capture logic means and responding to said match output by producing an event at said pin.
References Cited (Backward Citations)
US4222103A
Cited
US4326247A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-07-16 | 1994-01-15 | 1994-07-17 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-07-16 | 1998-01-15 | 1998-07-17 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-07-16 | 2002-01-15 | 2002-07-17 | $7700.00 | Window Closed / Lapsed |