Patent US4942457A successfully refreshed from Google Patents.
US4942457A
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Circuit arrangement for processing video components
Assignee: Deutsche Thomson Brandt GmbH
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Filing: 1988-09-27
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Granted: 1990-07-17
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Expires: 2008-09-27
Abstract
Abstract A video signal processor as for generating a picture-in-picture signal, generates respective analog luminance components and first and second analog chrominance components. In order to reduce the system hardware and processing speed, multiplexing circuitry subsamples the luminance and chrominance components on a field basis to provide alternating fields of only luminance and only chrominance signal. The multiplexing circuitry further subsamples the chrominance components by providing groups of horizontal lines of only the first chrominance component alternating with groups of horizontal lines of only the second chrominance component.
Inventors
- 👤 Heinz-Werner Keesen
- 👤 Laurent Perdrieau
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 04:41
CPC Classifications
H; H04; H04N; H04N9/00; H04N9/64; H04N11/00; H04N11/06; H04N11/08; H04N9/641
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
163 words
A circuit arrangement for processing video signal components including an analog luminance component and first and second analog chrominance components, said circuit arrangement comprising: respective input terminals for receiving said analog luminance component and said first and second analog chrominance components; multiplexing means having first, second and third input terminals for respectively receiving said first and second analog chrominance components and said luminance component, and having an output terminal; and means coupled to said multiplexing means for conditioning said multiplexing means to provide at its output terminal, fields of video signal alternating between a field of said first and second analog chrominance components and a field of said analog luminance components and for conditioning said multiplexing means to provide said field of first and second analog chrominance components as successive groups of N horizontal lines of said first analog chrominance component alternating with groups of M horizontal lines of said second analog chrominance component where M and N are integers greater than one.
Claim 2
Dependent Claim
163 words
A circuit arrangement for processing video signal components including an analog luminance component and first and second analog chrominance components, said circuit arrangement comprising: respective input terminals for receiving said analog luminance component and said first and second analog chrominance components; multiplexing means having first, second and third input terminals for respectively receiving said first and second analog chrominance components and said luminance component, and having an output terminal; and means coupled to said multiplexing means for conditioning said multiplexing means to provide at its output terminal, fields of video signal alternating between a field of said first and second analog chrominance components and a field of said analog luminance components and for conditioning said multiplexing means to provide said field of first and second analog chrominance components as successive groups of N horizontal lines of said first analog chrominance component alternating with groups of M horizontal lines of said second analog chrominance component where M and N are integers greater than one.
Claim 3
Dependent Claim
19 words
The circuit arrangement set forth in claim 1 wherein the integers M and N are both equal to four.
Claim 4
Dependent Claim
153 words
The circuit arrangement set forth in claim 1 wherein said multiplexing means comprises: a first multiplexer having first and second input terminals for respectively receiving said first and second analog chrominance components, and having an output terminal; a second multiplexer having a first input terminal coupled to receive said analog luminance component and a second input terminal coupled to the output terminal fo the first multiplexer, said second multiplexer having an output terminal for providing output signal from said multiplexing means; and said means for conditioning the multiplexing means includes means for conditioning said second multiplexer to alternately couple its first and second input terminals to its output terminal at a rate of one half of video field frequence, and for conditioning said first multiplexer to alternately couple its first and second input terminals to its output terminal at a rate of F H /(M+N) where F H is the horizontal line frequency.
Claim 5
Dependent Claim
19 words
The circuit apparatus set forth in claim 3 wherein the values of M and N are equal to four.
Claim 6
Dependent Claim
22 words
The circuit apparatus set forth in claim 1 further including an analog-to-digital converter having an input terminal coupled to said multiplexing means.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-07-16 | 1994-01-15 | 1994-07-17 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-07-16 | 1998-01-15 | 1998-07-17 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-07-16 | 2002-01-15 | 2002-07-17 | $7700.00 | Window Closed / Lapsed |