Slow peripheral handshake interface circuit

Claim 2

A computer system comprising: a microprocessor for generating an address strobe signal and receiving an acknowledge signal; a peripheral device for receiving said address strobe signal and generating a handshake signal in response thereto; a D-type flip-flop having a data input connected to a first logic value source, a clock input for receiving said address strobe signal, a reset input, and a Q output; a two input AND gate, with inverting inputs and output, for receiving said handshake signal and the signal from said Q output and generating said acknowledge signal; and an inverter for receiving said handshake signal and having an output connected to said flip-flop reset input; wherein said Q output provides a first logic value which disables said AND gate and a second logic value which enables said AND gate; and wherein removal of said address strobe signal sets the Q output to said first value and removal of said handshake signal resets the Q output to said second value.

Claim 3

The system of claim 1 wherein said address strobe signal, handshake signal and acknowledge signal are each active low signals, and wherein said first logic value is high and said second logic value is low.

Claim 6

The system of claim 3 wherein said means includes a latch.

Claim 7

The system of claim 4 wherein said latch is a D-type flip-flop having a data input connected to a first logic value source, a clock input, a reset input, and a Q output.

Claim 8

The system of claim 5 wherein said clock input receives said request signal, said reset input receives said handshake signal, and said Q output provides said control signal.

Claim 9

The system of claim 6 wherein said request signal, handshake signal and acknowledge signal are each active low signals.

Claim 10

The system of claim 7 wherein the first value of said control signal is high and the second value is low.

Claim 11

The system of claim 3 wherein said gate is a coincidence gate.

Claim 12

The system of claim 9 wherein said gate two input AND gate, with inverting inputs and output.

Claim 13

The system of claim 5 further comprising an inverter for receiving said handshake signal and having an output connected to said reset input.

Claim 14

The system of claim 3 wherein said first device is a micro processor and said second device is a peripheral.

Claim 15

The system of claim 11 wherein said request signal is an address strobe signal.

Claim 16

An interface circuit between a requesting device and a responding device comprising: means for receiving a request signal from said request device and a handshake signal from said responding device and generating a control signal in response thereto, wherein removal of said request signal sets said control signal to a first value and removal of said handshake signal resets said control signal to a second value; and a gate for generating an acknowledge signal, said gate having a first input connected to receive said control signal and a second input for receiving said handshake signal, said gate being disabled when said control signal is set to said first value and being enabled when said control signal is reset to said second value.

Claim 17

An interface circuit between a requesting device and a responding device comprising: means for receiving a request signal from said request device and a handshake signal from said responding device and generating a control signal in response thereto, wherein removal of said request signal sets said control signal to a first value and removal of said handshake signal resets said control signal to a second value; and a gate for generating an acknowledge signal, said gate having a first input connected to receive said control signal and a second input for receiving said handshake signal, said gate being disabled when said control signal is set to said first value and being enabled when said control signal is reset to said second value.

Claim 18

The system of claim 14 wherein said means is a D-type flip-flop having a data input for receiving a first logic value, a clock input for receiving said request signal, a reset input for receiving said handshake signal, and a Q output for providing said control signal.

Claim 19

The system of claim 15 wherein said request signal, handshake signal and acknowledge signal are each active low signals.

Claim 20

The system of claim 16 wherein the first value of said control signal is high and the second value is low.

Claim 21

The system of claim 14 wherein said gate is a coincidence gate.

Claim 22

The system of claim 18 wherein said gate is a two input AND gate, with inverting inputs and output.

Claim 23

The system of claim 15 further comprising an inverter for receiving said handshake signal and having an output connected to said reset input.

Claim 24

An interface circuit between a requesting device and a responding device comprising: an inverter for receiving a handshake signal from said responding device and generating an inverted handshake signal; a D-type flip-flop having a data input connected to receive a first logic value, a clock input for receiving a request signal from said requesting device, a reset input connected to receive said inverted handshake signal, and a Q output for generating a control signal, wherein removal of said request signal sets said control signal to a first value and removal of said inverted handshake signal resets said control signal to a second value; and a two input AND gate for generating an acknowledge signal for said requesting device, said gate having a first inverting input connected to receive said control signal, a second inverting input connected to receive said inverted handshake signal, and an inverting output, said gate being disabled when said control signal is set to said first value and being enabled when said control signal is reset to said second value; wherein said request signal, handshake signal and acknowledge signal are each active low signals, and said first logic value is high and said second logic value is low.

Claim 25

An interface circuit between a requesting device and a responding device comprising: an inverter for receiving a handshake signal from said responding device and generating an inverted handshake signal; a D-type flip-flop having a data input connected to receive a first logic value, a clock input for receiving a request signal from said requesting device, a reset input connected to receive said inverted handshake signal, and a Q output for generating a control signal, wherein removal of said request signal sets said control signal to a first value and removal of said inverted handshake signal resets said control signal to a second value; and a two input AND gate for generating an acknowledge signal for said requesting device, said gate having a first inverting input connected to receive said control signal, a second inverting input connected to receive said inverted handshake signal, and an inverting output, said gate being disabled when said control signal is set to said first value and being enabled when said control signal is reset to said second value; wherein said request signal, handshake signal and acknowledge signal are each active low signals, and said first logic value is high and said second logic value is low.