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US4497041A Expired / Lapsed US ⏱️ 0.0 years remaining

Parallel serial controller

Assignee: ABC/SEBRN TECHCORP Inc
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Filing: 1982-09-02
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Granted: 1985-01-29
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Expires: 2002-09-02
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Abstract

Abstract A computer-peripheral interface includes a latch to receive parallel data from a peripheral, such as a cash register, with a hardware mask to reject irrelevant data, a simple FIFO memory and a parallel-serial converter for transmission to a controlling computer. These devices are controlled by a combination of five one-shots for timing, and a D flip-flop and gates. The problem of controlling a variety of peripherals, such as cash registers, by a central computer without also incorporating microprocessors or equivalent complicated devices in each peripheral yet still providing sufficient data handling capacity is solved.

Inventors

  • 👤 Leon Braun

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-30 06:52
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/38; G06F13/42; G06F13/4204; G06F13/4208; G06F13/4213

Claims Analysis

Total Claims: 4
Claim 1
Independent Claim 407 words
An interface between a peripheral output and a computer, where the peripheral outputs data in the form of a series of n-bit words with corresponding strobe pulses and certain of the said n-bit words are to be masked and where said interface comprises, (a) an n-bit word D flip-flop connected to said peripheral output thereby receiving said n-bit words at an input thereof; (b) a first one-shot means, said first one-shot means being triggered by said strobe pulses to deliver a first one-shot output, said first one-shot output activating said D flip-flop to generate a D flip-flop output after a time delay sufficiently long to have said n-bit peripheral output word set up on said D flip-flop inputs; (c) an n-bit word first-in/first-out memory, said memory connected to said D flip-flop output to receive said output as a memory input; (d) a hardware mask for detecting said certain of said n-bit words which are to be disregarded, said mask being connected to said D flip-flop so that the output thereof becomes the mask input; (e) logic means preselected in said mask to differentiate such n-bit words as are desired and those to be disregarded; (f) said mask having a mask output that is preselected to desired or to be disregarded n-bit words; (g) a second one-shot means triggered by said strobe pulses to deliver a second one-shot output, said second one-shot output being combined with said mask output and triggering said memory to store the n-bit word on said memory input if and only if said mask output indicates that said n-bit word on said memory input is not one of said certain n-bit words to be disregarded thereby storing a series of n-bit words; (h) a third one-shot triggered by said strobe pulses to deliver a third one shot output, said third one-shot output having a pulse width exceeding the time between successive strobe pulses in a said series so that during a said series said third one-shot output forms a single pulse; (i) said memory having a not empty indicator output connected to said third one-shot output; (j) said not empty indicator output being combined with said third one-shot output to block any strobe pulse from said peripheral if said memory has words in storage and said any strobe pulse is not one of a said series; (k) means for said computer to communicate with said memory and receive said series of n-bit memory words.
Claim 2
Dependent Claim 407 words
An interface between a peripheral output and a computer, where the peripheral outputs data in the form of a series of n-bit words with corresponding strobe pulses and certain of the said n-bit words are to be masked and where said interface comprises, (a) an n-bit word D flip-flop connected to said peripheral output thereby receiving said n-bit words at an input thereof; (b) a first one-shot means, said first one-shot means being triggered by said strobe pulses to deliver a first one-shot output, said first one-shot output activating said D flip-flop to generate a D flip-flop output after a time delay sufficiently long to have said n-bit peripheral output word set up on said D flip-flop inputs; (c) an n-bit word first-in/first-out memory, said memory connected to said D flip-flop output to receive said output as a memory input; (d) a hardware mask for detecting said certain of said n-bit words which are to be disregarded, said mask being connected to said D flip-flop so that the output thereof becomes the mask input; (e) logic means preselected in said mask to differentiate such n-bit words as are desired and those to be disregarded; (f) said mask having a mask output that is preselected to desired or to be disregarded n-bit words; (g) a second one-shot means triggered by said strobe pulses to deliver a second one-shot output, said second one-shot output being combined with said mask output and triggering said memory to store the n-bit word on said memory input if and only if said mask output indicates that said n-bit word on said memory input is not one of said certain n-bit words to be disregarded thereby storing a series of n-bit words; (h) a third one-shot triggered by said strobe pulses to deliver a third one shot output, said third one-shot output having a pulse width exceeding the time between successive strobe pulses in a said series so that during a said series said third one-shot output forms a single pulse; (i) said memory having a not empty indicator output connected to said third one-shot output; (j) said not empty indicator output being combined with said third one-shot output to block any strobe pulse from said peripheral if said memory has words in storage and said any strobe pulse is not one of a said series; (k) means for said computer to communicate with said memory and receive said series of n-bit memory words.
Claim 3
Dependent Claim 38 words
The interface of claim 1, wherein said communication means comprises: (a) a parallel-serial converter for converting n-bit words to serial format and connected to said memory; and (b) a bi-directional balanced line connecting said converter to said computer.
Claim 4
Dependent Claim 42 words
The interface of claim 2, wherein said converter has an individual address so that said line may be connected to a plurality of such interfaces and permit said computer to individually communicate with each interface using an individual address for each interface.

References Cited (Backward Citations)

US3631403A Cited
US3699532A Cited
US3921148A Cited
US4058680A Cited
US4082922A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1988-01-29 1988-07-30 1989-01-29 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1992-01-29 1992-07-30 1993-01-29 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1996-01-29 1996-07-30 1997-01-29 $7700.00 Window Closed / Lapsed

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