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US4941153A
Expired / Lapsed
US
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High-speed digital data communication system
Assignee: Microelectronics Technology Inc
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Filing: 1987-08-25
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Granted: 1990-07-10
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Expires: 2007-08-25
Abstract
Abstract According to the invention, a high-speed digital data communication system employs current mode circuitry as input and output devices at the ends of a transmission line, such as the interconnections between integrated circuit chips. Specifically, a current mode driver switch generates output current amplitudes responsive to a source of a digital signal representative of data to be transmitted. The switch output is connected to the input of a transmission line. The output of the transmission line is connected to the input of a receiving circuit that responds to the current amplitudes and has an input at an approximately constant voltage level. The receiving circuit is a transistor connected in a common base configuration. The emitter of the transistor is connected to the output of the transmission line. The base of the transistor is connected to a constant voltage source. A pulse shaper in the form of a Schmitt trigger has positive feedback from output to input. The described current mode circuitry is incorporated into an integrated circuit chip.
Inventors
- 👤 Edwin A. Kelley
- 👤 Wade J. Stone
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 19:56
CPC Classifications
H; H04; H04L; H04L25/00; H04L25/02
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
160 words
A high speed digital data communication system comprising: a source of a digital signal representative of data to be transmitted; a current mode driver switch for generating a current reponse to the source signal representative of the data; a transmission line having an input terminal and an output terminal; means for connecting the switch to the input terminal of the transmission line; a receiving circuit responding to the current amplitudes and having an input terminal wherein said receiving circuit comprises an approximately constant voltage source and a transistor connected in a common base configuration, the emitter of the transistor being connected to the output terminal of the transmission line and the base of the transistor being connected to the constant voltage source, whereby the transistor input impedance functions as the termination to the transmission line; means for terminating said transmission line; and means for connecting the output terminal of the transmission line to the input terminal of the receiving circuit.
Claim 2
Dependent Claim
160 words
A high speed digital data communication system comprising: a source of a digital signal representative of data to be transmitted; a current mode driver switch for generating a current reponse to the source signal representative of the data; a transmission line having an input terminal and an output terminal; means for connecting the switch to the input terminal of the transmission line; a receiving circuit responding to the current amplitudes and having an input terminal wherein said receiving circuit comprises an approximately constant voltage source and a transistor connected in a common base configuration, the emitter of the transistor being connected to the output terminal of the transmission line and the base of the transistor being connected to the constant voltage source, whereby the transistor input impedance functions as the termination to the transmission line; means for terminating said transmission line; and means for connecting the output terminal of the transmission line to the input terminal of the receiving circuit.
Claim 3
Dependent Claim
27 words
The digital data communication system of claim 1, in which the receiving circuit additionally comprises a pulse shaping circuit connected to the collector of the receiving transistor.
Claim 4
Dependent Claim
78 words
The digital data communication system of claim 1, in which the pulse shaping circuit comprises a pair of transistors with emitters connected together and load resistors connected from the respective collectors of the transistor pair to a common node, a common resistor connected at one end to the common node, and means for biasing the transistor pair so the sum of the currents through them remains approximately constant, whereby the common node serves as the constant voltage source.
Claim 5
Dependent Claim
20 words
The digital data communication system of claim 3, in which the biasing means including means for compensating for temperature changes.
Claim 6
Dependent Claim
44 words
The digital data communication system of claim 3, in which the base of one paired transistor is connected to the collector of the other paired transistor and the collector of the common base transistor is connected to the base of the other paired transistor.
Claim 7
Dependent Claim
48 words
The digital data communication system of claim 1, in which the current mode driver switch comprises a pair of transistors with emitters connected together, the collector of one transistor being connected to the transmission line and the collector of the other transistor being connected to a reference potential.
Claim 8
Dependent Claim
26 words
The digital data communication system of claim 6, in which the souce is a bipolar voltage signal connected to the respective bases of the transistor pair.
References Cited (Backward Citations)
US3105198A
Cited
US3375457A
Cited
US4450571A
Cited
US4326287A
Cited
US4607232A
Cited
US4713827A
Cited
US4736385A
Cited
US4755767A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-07-09 | 1994-01-08 | 1994-07-10 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-07-09 | 1998-01-08 | 1998-07-10 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-07-09 | 2002-01-08 | 2002-07-10 | $7700.00 | Window Closed / Lapsed |