Floating point normalization and rounding prediction circuit

Claim 2

A circuit for normalizing floating point arithmetic results of certain predetermined types, and for predicting whether rounding is necessary by examination of predetermined bits in the arithmetic result, comprising (a) means for detecting arithmetic operations of the multiply type, and addition of operands of same sign, and subtraction of operands of different signs, and activating a transfer sequence in response thereto; (b) said transfer sequence including means for examining the two most significant bits of the result fraction and completing a transfer of the fraction and exponent result into a register according to the following procedure: (i) if a multiply type and the two most significant fraction bits are of the form 1.X, transfer the results directly into said register, and increase the exponent by one; (ii) if a multiply type and the two most significant fraction bits are of the form 0.1, transfer the fractional result into said register with a 1-bit left shift, and transfer the exponent directly, unchanged, into said register; (iii) if an addition or subtraction type and the two most significant fraction bits are of the form 1.X, transfer the results directly into said register; and (iv) if an addition or subtraction type and the two most significant fraction bits are of the form 1X., transfer the fractional results directly into said register; with a 1-bit right shift, and transfer the exponent, increased by one, into said register.

Claim 3

The circuit of claim 1, further comprising means for examining the result sign bit, least significant bit, guard bit, round bit and sticky bit; and means for detecting the rounding mode selected for the arithmetic operation; and means for predicting whether a rounding of the fractional result is necessary as a consequence of said examination of result sign bit, least significant bit, guard bit, round bit and sticky bit, and said means for detecting the rounding mode selected.

Claim 4

The circuit of claim 2, further comprising means for skipping the rounding as result of said means for predicting.

Claim 5

The circuit of claim 3, wherein said means for predicting further comprises a plurality of logic circuits coupled to said means for examining the result sign bit, least significant bit, guard bit, round bit and sticky bit, and coupled to said means for detecting the selected rounding mode, said plurality of logic circuits including a decision network for activating said means for skipping round according to the following tabulation, where "No" signifies skipping rounding: ______________________________________ S L I S G Rounding Mode B G R S N Nearest Pos Inf Neg Inf Zero ______________________________________ 0 0 0 0 0 No No No No 0 0 0 1 0 No Yes No No 0 0 1 0 0 No Yes No No 0 0 1 1 0 No Yes No No 0 1 0 0 0 No Yes No No 0 1 0 1 0 Yes Yes No No 0 1 1 0 0 Yes Yes No No 0 1 1 1 0 Yes Yes No No 1 0 0 0 0 No No No No 1 0 0 1 0 No Yes No No 1 0 1 0 0 No Yes No No 1 0 1 1 0 No Yes No No 1 1 0 0 0 Yes Yes No No 1 1 0 1 0 Yes Yes No No 1 1 1 0 0 Yes Yes No No 1 1 1 1 0 Yes Yes No No 0 0 0 0 1 No No No No 0 0 0 1 1 No No Yes No 0 0 1 0 1 No No Yes No 0 0 1 1 1 No No Yes No 0 1 0 0 1 No No Yes No 0 1 0 1 1 Yes No Yes No 0 1 1 0 1 Yes No Yes No 0 1 1 1 1 Yes No Yes No 1 0 0 0 1 No No No No 1 0 0 1 1 No No Yes No 1 0 1 0 1 No No Yes No 1 0 1 1 1 No No Yes No 1 1 0 0 1 Yes No Yes No 1 1 0 1 1 Yes No Yes No 1 1 1 0 1 Yes No Yes No 1 1 1 1 1 Yes No Yes No. ______________________________________