Temperature compensated monolithic delay circuit

Claim 2

A timing circuit, comprising: a capacitor; a first field-effect transistor, comprising a gate, connected to discharge said capacitor; an additional stage, connected to said capacitor and configured to change state when said capacitor is discharged to a predetermined voltage; a plurality of bipolar transistors, connected to reduce a temperature-independent reference voltage by a multiple of the base-emitter voltage drop of one of said plurality of bipolar transistors, to provide a temperature-dependent reference potential; a second field-effect transistor, having source and drain terminals con between a first current source and said temperature-dependent reference potential having a gate connected to said drain terminal thereof; said gate of said first field-effect transistor being coupled to said gate of said second field-effect transistor so that said gate of said first field-effect transistor receives a voltage corresponding to the voltage on said gate of said second field-effect transistor.

Claim 3

The circuit of claim 1 wherein said additional stage consists essentially of a comparator.

Claim 4

The circuit of claim 1, wherein said gate of said first field-effect transistor is coupled to said gate of said second field-effect transistor through a buffer amplifier.

Claim 5

The circuit of claim 1, wherein said gate of said first field-effect transistor is coupled to the output of a buffer amplifier having unity gain and low source impedance, and the input of said buffer amplifier is connected to said gate of said second field-effect transistor.

Claim 6

The circuit of claim 1, wherein said temperature-independent reference voltage is derived from a bandgap voltage reference.

Claim 7

The circuit of claim 1, further comprising a switching transistor connected to rapidly charge said capacitor.

Claim 8

The circuit of claim 1, further comprising a plurality of second current sources, each of said second current sources being connected to keep a respective one of said bipolar transistors operating in its active region.

Claim 9

The circuit of claim 1, wherein a first one of said plurality of bipolar transistors comprises a base, connected to said temperature-independent reference voltage, and an emitter; and a second one of said plurality of bipolar transistors comprises a base, connected to said emitter of said first bipolar transistor.

Claim 10

The circuit of claim 1, wherein said plurality of bipolar transistors are NPN transistors.

Claim 11

The circuit of claim 1, wherein said plurality of bipolar transistors comprises at least three bipolar transistors, and is connected to reduce the temperature-independent reference voltage by at least three times the base-emitter voltage drop of one of said bipolar transistors, to provide said temperature-dependent reference potential.

Claim 12

The circuit of claim 1, wherein said plurality of bipolar transistors comprises exactly three bipolar transistors, and is connected to reduce the temperature-independent reference voltage by exactly three times the base-emitter voltage drop of one of said bipolar transistors, to provide said temperature-dependent reference potential.

Claim 13

A timing circuit, comprising: a capacitor; a first field-effect transistor, comprising a gate, connected to discharge said capacitor; an additional stage, connected to said capacitor and configured to change state when said capacitor is discharged to a predetermined voltage; a bias voltage generating circuit, comprising multiple bipolar transistors and a second field-effect transistor, coupled to said gate of said first field-effect transistor to provide a bias voltage which is equal to: the sum of a temperature-independent reference voltage and the threshold voltage of said second field-effect transistor, reduced by the combined base-emitter voltage drops of said multiple bipolar transistors.

Claim 14

A timing circuit, comprising: a capacitor; a first field-effect transistor, comprising a gate, connected to discharge said capacitor; an additional stage, connected to said capacitor and configured to change state when said capacitor is discharged to a predetermined voltage; a bias voltage generating circuit, comprising multiple bipolar transistors and a second field-effect transistor, coupled to said gate of said first field-effect transistor to provide a bias voltage which is equal to: the sum of a temperature-independent reference voltage and the threshold voltage of said second field-effect transistor, reduced by the combined base-emitter voltage drops of said multiple bipolar transistors.

Claim 15

The circuit of claim 12, wherein said additional stage consists essentially of a comparator.

Claim 16

The circuit of claim 12, wherein said gate of said first field-effect transistor is connected to receive said bias voltage from a buffer amplifier having unity gain and low source impedance.

Claim 17

The circuit of claim 12, wherein said temperature-independent reference voltage is derived from a bandgap voltage reference.

Claim 18

The circuit of claim 12, further comprising a switching transistor connected to rapidly charge said capacitor.

Claim 19

An integrated circuit, comprising: at least one timing circuit, comprising: a capacitor; a first field-effect transistor, comprising a gate, connected to discharge said capacitor; a switching transistor connected to rapidly charge said capacitor. an additional stage, connected to said capacitor and configured to change state when said capacitor is discharged to a predetermined voltage; wherein the gate of said first field-effect transistor is connected to receive a bias voltage which is equal to: the sum of a temperature-independent reference voltage and the threshold voltage of said second field-effect transistor, reduced by the combined base-emitter voltage drops of said multiple bipolar transistors; said timing circuit being connected so that the leading edge of an incoming pulse will turn on said switching transistor, and the trailing edge of the incoming pulse will turn off said switching transistor; whereby said timing circuit will add a precisely predetermined delay onto the trailing edge of each said pulse.

Claim 20

An integrated circuit, comprising: at least one timing circuit, comprising: a capacitor; a first field-effect transistor, comprising a gate, connected to discharge said capacitor; a switching transistor connected to rapidly charge said capacitor. an additional stage, connected to said capacitor and configured to change state when said capacitor is discharged to a predetermined voltage; wherein the gate of said first field-effect transistor is connected to receive a bias voltage which is equal to: the sum of a temperature-independent reference voltage and the threshold voltage of said second field-effect transistor, reduced by the combined base-emitter voltage drops of said multiple bipolar transistors; said timing circuit being connected so that the leading edge of an incoming pulse will turn on said switching transistor, and the trailing edge of the incoming pulse will turn off said switching transistor; whereby said timing circuit will add a precisely predetermined delay onto the trailing edge of each said pulse.

Claim 21

The circuit of claim 17, wherein said additional stage consists essentially of a comparator.

Claim 22

The circuit of claim 17, wherein said gate of said first field-effect transistor is connected to receive said bias voltage from a buffer amplifier having unity gain and low source impedance.

Claim 23

The circuit of claim 17, wherein said temperature-independent reference voltage is derived from a bandgap voltage reference.

Claim 24

A timing circuit, comprising: a capacitor; a first field-effect transistor, comprising a gate, connected to discharge said capacitor; a switching transistor connected to rapidly charge said capacitor; a comparator, connected to said capacitor; a plurality of bipolar transistors, connected to reduce a bandgap-derived reference voltage by a multiple of the base-emitter voltage drop of one of said plurality of bipolar transistors, to provide a temperature-dependent reference potential; a plurality of first current sources, each of said second current sources being connected to keep a respective one of said bipolar transistors operating in its active region; a second field-effect transistor, having source and drain terminals connected between a second current source and said temperature-dependent reference potential, and having a gate connected to said drain terminal thereof; said gate of said first field effect transistor being coupled to said gate of said second field-effect transistor so that said gate of said first field-effect transistor receives a voltage corresponding to the voltage on said gate of said second field-effect transistor.

Claim 25

A timing circuit, comprising: a capacitor; a first field-effect transistor, comprising a gate, connected to discharge said capacitor; a switching transistor connected to rapidly charge said capacitor; a comparator, connected to said capacitor; a plurality of bipolar transistors, connected to reduce a bandgap-derived reference voltage by a multiple of the base-emitter voltage drop of one of said plurality of bipolar transistors, to provide a temperature-dependent reference potential; a plurality of first current sources, each of said second current sources being connected to keep a respective one of said bipolar transistors operating in its active region; a second field-effect transistor, having source and drain terminals connected between a second current source and said temperature-dependent reference potential, and having a gate connected to said drain terminal thereof; said gate of said first field effect transistor being coupled to said gate of said second field-effect transistor so that said gate of said first field-effect transistor receives a voltage corresponding to the voltage on said gate of said second field-effect transistor.