US4939384A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Flip-flop circuit
Assignee: Oki Electric Industry Co Ltd
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Filing: 1988-10-03
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Granted: 1990-07-03
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Expires: 2008-10-03
Abstract
Abstract A flip-flop circuit comprises two basic flip-flop circuits, four field effect transistors, and four amplifiers. The two basic flip-flop circuits respectively composed of a first and a second inverter circuits, and an output terminal of the first inverter circuit is connected to an input terminal of the second inverter circuit and an output terminal of the second inverter circuit is connected to the input terminal of the first inverter circuit. The field effect transistors have sources respectively connected to input terminals of the two basic flip-flop circuits, and gates to which clock pulses and inverse clock pulses are applied. The amplifiers respectively composed of an inverter circuit are connected to output terminals of the two basic flip-flop circuits.
Inventors
- 👤 Makoto Shikata
- 👤 Koutaro Tanaka
- 👤 Masahiro Akiyama
- 👤 Yasushi Kawakami
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 14:21
CPC Classifications
H; H03; H03K; H03K3/00; H03K3/02; H03K3/353; H03K3/356; H03K3/356017; H03K3/356052; H03K3/35606; H03K3/027; H03K3/037
Claims Analysis
Total Claims: 2
Claim 1
Independent Claim
204 words
A flip-flop circuit comprising: (a) a first and a second basic flip-flop circuits each composed of two inverter circuits respectively having an output terminal being connected to an input terminal of the other inverter circuit; (b) first two field effect transistors each having a source connected to the input terminal of each inverter circuit of the first basic flip-flop circuit, a drain connected respectively to a data input terminal and an inverse data input terminal, and a gate to which inverse clock pulses are applied; (c) second two field effect transistors each having a source connected to the input terminal of each inverter circuit of the second basic flip-flop circuit, and a gate to which clock pulses are applied; (d) first two amplifiers each composed of an inverter circuit having an input terminal connected to each source of the first two field effect transistors, and an output terminal connected to each drain of the second field effect transistors; and (e) second two amplifiers each composed of an inverter circuit having an input terminal connected to each source of the second two field effect transistors, an output terminal and an inverse output terminal respectively connected to each drain of the first two field effect transistors.
Claim 2
Dependent Claim
204 words
A flip-flop circuit comprising: (a) a first and a second basic flip-flop circuits each composed of two inverter circuits respectively having an output terminal being connected to an input terminal of the other inverter circuit; (b) first two field effect transistors each having a source connected to the input terminal of each inverter circuit of the first basic flip-flop circuit, a drain connected respectively to a data input terminal and an inverse data input terminal, and a gate to which inverse clock pulses are applied; (c) second two field effect transistors each having a source connected to the input terminal of each inverter circuit of the second basic flip-flop circuit, and a gate to which clock pulses are applied; (d) first two amplifiers each composed of an inverter circuit having an input terminal connected to each source of the first two field effect transistors, and an output terminal connected to each drain of the second field effect transistors; and (e) second two amplifiers each composed of an inverter circuit having an input terminal connected to each source of the second two field effect transistors, an output terminal and an inverse output terminal respectively connected to each drain of the first two field effect transistors.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-07-02 | 1994-01-01 | 1994-07-03 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-07-02 | 1998-01-01 | 1998-07-03 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-07-02 | 2002-01-01 | 2002-07-03 | $7700.00 | Window Closed / Lapsed |