Memory access system utilizing address translation

Claim 2

A memory access system for receiving a logical address and a memory request, translating the logical address into a real address, and accessing a memory by using the real address, comprising: first transmitting means for transmitting a non-address-translation portion, which is not an object to be translated, in the logical address to said memory through an address signal line in advance when the memory request associated with the logical address supplied to said memory is generated; and second transmitting means for transmitting an address-translation portion, which is an object to be translated, in the logical address to said memory through said address signal line upon completion of address translation of the address-translation portion.

Claim 3

A memory access system comprising: an address register for respectively storing a logical page address and a logical intra-page address in upper and lower portions thereof; page address translation means for translating an output from the upper portion of said address register into a real page address and outputting a real page address signal representing the real page address and an address translation success signal representing that address translation is performed; a real page address register for storing the real page address signal output from said page address translation means; selector means responsive to a first control signal for selecting the output signal from the lower portion of said address register or the output signal from said real address register and outputting the selected signal as a memory address signal; a first register, controlled by a second control signal obtained by inverting the first control signal, for storing and outputting an intra-page address signal selected by said selector means; a second register, controlled by the first control signal, for storing and outputting the real page address signal selected by said selector means; first control signal generating means for generating the first control signal by using the address translation success signal and a signal representing a memory request, and outputting the first control signal to said selector means and said second register; and inverting means for inverting the first control signal to obtain the second control signal and outputting the second control signal to said first register.

Claim 4

A memory access system comprising: an address register for respectively storing a logical page address and a logical intra-page address in upper and lower portions thereof; page address translation means for translating an output from the upper portion of said address register into a real page address and outputting a real page address signal representing the real page address and an address translation success signal representing that address translation is performed; a real page address register for storing the real page address signal output from said page address translation means; selector means responsive to a first control signal for selecting the output signal from the lower portion of said address register or the output signal from said real address register and outputting the selected signal as a memory address signal; a first register, controlled by a second control signal obtained by inverting the first control signal, for storing and outputting an intra-page address signal selected by said selector means; a second register, controlled by the first control signal, for storing and outputting the real page address signal selected by said selector means; first control signal generating means for generating the first control signal by using the address translation success signal and a signal representing a memory request, and outputting the first control signal to said selector means and said second register; and inverting means for inverting the first control signal to obtain the second control signal and outputting the second control signal to said first register.

Claim 5

A memory access system according to claim 2, wherein said first control signal generating means generates the first control signal such that, when the memory request has occurred and the logical address is loaded on said address register, the first control signal is non-active and said selector selects the output signal from the lower portion of said address register, thereby causing said first register to store the intra-page address, then, when the address translation success signal is supplied thereto, the first control signal becomes active to render said selector to select the output signal from the real address register, thereby causing said second register to store the real page address signal while said first register holds the intra-page address, and then said first and second registers simultaneously output the intra-page address signal and the real page address signal, respectively.