Solid-state imaging device with static induction transistor matrix

Claim 2

A solid-state imaging device comprising: a plurality of static induction transistors arranged in a matrix-like manner between a plurality of row lines and a plurality of vertical signal lines, each of which is connected to a row line with the gate electrode thereof and to a vertical signal line with one principal electrode thereof; drive transistors connected to each of said plurality of vertical signal lines through respective sample transistors; drive means for simultaneously reading out during a predetermined readout period the signals stored in said static induction transistors, in accordance with row selection signals to be applied to said row lines, holding said signals in the gates of said drive transistors through the drain-source paths of said sample transistors, and successively reading out within the horizontal scanning period the signals thus held; and spurious signal generation preventing means for preventing generation of spurious signals due to the ON-operation of the static induction transistors connected to those row lines to which said row selection signal is not applied.

Claim 3

A solid-state imaging device as claimed in claim 1, wherein said spurious signal generation preventing means consist of clamping means for clamping the gate potentials of all the static induction transistors at a predetermined potential during the periods excluding said predetermined readout period.

Claim 4

A solid-state imaging device as claimed in claim 2, wherein said clamping means consist of resetting MOS transistors, each of said MOS transistor being connected at one main electrode thereof to a vertical signal line, and grounded at the other main electrode, with the gate being impressed with a vertical signal line resetting pulse.

Claim 5

A solid-state imaging device as claimed in claim 2, wherein said predetermined readout period is set shorter than the period for the clamping effected by said clamping means.

Claim 6

A solid-state imaging device as claimed in claim 2, wherein said predetermined readout period and the point of time at which the signals read out during the period are held by said drive transistors are set within the horizontal blanking period, the period for the clamping effected by said clamping means being set within said horizontal scanning period.

Claim 7

A solid-state imaging device as claimed in claim 4, wherein said predetermined readout period and the point of time at which the signals read out during the period are held by said drive transistors are set within the horizontal blanking period, the period for the clamping effected by said clamping means being set within said horizontal scanning period.

Claim 8

A solid-state imaging device as claimed in claim 1, wherein said spurious signal generation preventing means consist of charging means for charging the parasitic capacitance connected to said vertical signal lines up to a predetermined level before applying said selection signal.

Claim 9

A solid-state imaging device as claimed in claim 7, wherein said charging means consist of MOS transistors, each of said MOS transistors being connected at one end to a power source with a predetermined voltage and at the other end to one of said vertical signal lines.

Claim 10

A solid-state imaging device as claimed in claim 7, wherein said charging means consist of static induction transistors, each of said static induction transistors being connected at one end to a power source with a predetermined voltage and at the other end to one of said vertical signal lines.

Claim 11

A solid-state imaging device as claimed in claim 7, wherein said charging means consist of resetting MOS transistors each of which is connected to a vertical signal line at one main electrode thereof and impressed with a precharging pulse at the other main electrode, with the gate being impressed with a vertical signal line resetting pulse.

Claim 12

A solid-state imaging device comprising: a plurality of static induction transistors arranged in a matrix-like manner between a plurality of row lines and a plurality of vertical signal lines, each of which is connected to a row line with the gate electrode thereof and to a vertical signal line with one principal electrode thereof; capacitors connected to each of said plurality of vertical signal lines through respective sample transistors; drive means for simultaneously reading out during a predetermined readout period the signals stored in said static induction transistors, in accordance with row selection signals to be applied to said row lines, holding said signals in said capacitors, said signals input to said capacitors through said sample transistors, and successively reading out within the horizontal scanning period the signals thus held; and spurious signal generation preventing means for preventing generation of spurious signals due to the ON-operation of the static induction transistors connected to those row lines to which said row selection signal is not applied, wherein said spurious signal generation means includes charging means for the parasitic capacitance connected to said vertical signal lines up to a predetermined level before applying said selection signal and wherein said charging means includes MOS transistors, each of said MOS transistors being connected at one end to a power source with a predetermined voltage and at the other end to one said vertical signal lines.

Claim 13

A solid-state imaging device comprising: a plurality of static induction transistors arranged in a matrix-like manner between a plurality of row lines and a plurality of vertical signal lines, each of which is connected to a row line with the gate electrode thereof and to a vertical signal line with one principal electrode thereof; capacitors connected to each of said plurality of vertical signal lines through respective sample transistors; drive means for simultaneously reading out during a predetermined readout period the signals stored in said static induction transistors, in accordance with row selection signals to be applied to said row lines, holding said signals in said capacitors, said signals input to said capacitors through said sample transistors, and successively reading out within the horizontal scanning period the signals thus held; and spurious signal generation preventing means for preventing generation of spurious signals due to the ON-operation of the static induction transistors connected to those row lines to which said row selection signal is not applied, wherein said spurious signal generation means includes charging means for the parasitic capacitance connected to said vertical signal lines up to a predetermined level before applying said selection signal and wherein said charging means includes MOS transistors, each of said MOS transistors being connected at one end to a power source with a predetermined voltage and at the other end to one said vertical signal lines.