Abstract A packet data switch for transferring data packets including an address part and an information part from one of a plurality of incoming data links (10,30,50) to one or more outgoing data links (22, 42, 62) and supplying new address information for each data packet on the outgoing links. The selector includes a separate memory means (e.g. 13) for each incoming data link (10, 30, 50) and a separate memory means (e.g. 20) for each outgoing data link (22, 42, 62). The memory means assigned to the incoming data links send control signals for selective writing of a data packet into one or more buffer registers (e.g. 19) which are each assigned to an outgoing link (e.g. 22). The memory means assigned to the outgoing links supply the new address information for the data packets to the outgoing links.
A packet data switch for transferring data packets, having an address portion and an information portion, from a plurality of incoming data links to a plurality of outgoing data links, which comprises: a plurality of first means, each of which is assigned to an incoming data link, said first means including a buffer register for incoming data packets and a first memory means, each of said first memory means generating control signals; and a plurality of second means, each of which is connected to said plurality of first means and is assigned to an outgoing data link, said second means including a second memory means and a buffer register for selectively writing-in incoming data packets in response to the control signals from said first memory means, said second memory means supplying new address information to the incoming data packets which are then provided to the outgoing data links.
Claim 2
Dependent Claim
148 words
A packet data switch for transferring data packets, having an address portion and an information portion, from a plurality of incoming data links to a plurality of outgoing data links, which comprises: a plurality of first means, each of which is assigned to an incoming data link, said first means including a buffer register for incoming data packets and a first memory means, each of said first memory means generating control signals; and a plurality of second means, each of which is connected to said plurality of first means and is assigned to an outgoing data link, said second means including a second memory means and a buffer register for selectively writing-in incoming data packets in response to the control signals from said first memory means, said second memory means supplying new address information to the incoming data packets which are then provided to the outgoing data links.
Claim 3
Dependent Claim
31 words
A packet data switch according to claim 1 wherein said second memory means further includes an additional buffer register in which each data packet is provided with the new address information.