Subthreshold CMOS amplifier with offset adaptation

Claim 2

An analog MOS inverting amplifier fabricated as a part of an integrated circuit, said amplifier having a gain of magnitude much larger than 1, including: an output node, an inverting input node, said input node being a floating node forming the gate of at least one MOS transistor, a first capacitor for coupling an input to said circuit to said floating node, a second capacitor connected from said output node to said floating node, an opaque layer covering portions of the surface of said integrated circuit containing active circuits, said opaque layer having an aperture therein above said second capacitor for allowing ultraviolet light to fall onto both electrodes of said second capacitor whereby the offset voltage of said amplifier can be adapted while a source of ultraviolet light is present.

Claim 3

An analog MOS inverting amplifier fabricated as a part of an integrated circuit, said amplifier having a gain of magnitude much larger than 1, including: an output node, a noninverting input node, an inverting input node, said inverting input node being a floating node and forming the gate of at least one MOS transistor, a first capacitor for coupling an input to said floating node, a second capacitor connected from said output node to said floating node, an opaque layer covering portions of the surface of said integrated circuit containing active circuits, said opaque layer having an aperture therein above said second capacitor for allowing ultraviolet light to fall onto both electrodes of said second capacitor whereby the offset voltage of said amplifier can be adapted while a source of ultraviolet light is present.

Claim 4

An analog MOS inverting amplifier fabricated as a part of an integrated circuit, said amplifier having a gain of magnitude much larger than 1, including: an output node, a noninverting input node, an inverting input node, said inverting input node being a floating node and forming the gate of at least one MOS transistor, a first capacitor for coupling an input to said floating node, a second capacitor connected from said output node to said floating node, an opaque layer covering portions of the surface of said integrated circuit containing active circuits, said opaque layer having an aperture therein above said second capacitor for allowing ultraviolet light to fall onto both electrodes of said second capacitor whereby the offset voltage of said amplifier can be adapted while a source of ultraviolet light is present.

Claim 5

The amplifier of claim 2, further including means for selectively connecting together said input and said non-inverting input node.

Claim 6

The amplifier of claim 2 further including a pass gate having a first node connected to said inverting input node, a second node connected to said non-inverting input node, and a pass input.

Claim 9

An analog MOS differential amplifier fabricated as a part of an integrated circuit, said amplifier having a gain of magnitude much larger than 1, including: a non-inverting input node, an inverting input node, an output node, a floating node, a first MOS input transistor, having its gate connected to said non-inverting input node, a second MOS input transistor, having its gate connected to said floating node, and its source connected to the source of said first MOS input transistor, current source means for supplying a bias current to the source of said first and second MOS input transistors, current mirror means, connected to the drains of said first and second MOS N-channel input transistors, for developing an output voltage proportionate to the difference between currents flowing in the drains of said first and second MOS input transistors, a first capacitor having a first electrode connected to said inverting input node and a second electrode connected to said floating node, a second capacitor having a first electrode connected to said output node and a second electrode connected to said floating node, an opaque layer covering portions of the surface of said integrated circuit containing active circuits, said opaque layer having an aperture therein above said second capacitor for allowing ultraviolet light to fall onto said first and second electrodes of said second capacitor whereby the offset voltage of said amplifier can be adapted while a source of ultraviolet light is present.

Claim 10

An analog MOS differential amplifier fabricated as a part of an integrated circuit, said amplifier having a gain of magnitude much larger than 1, including: a non-inverting input node, an inverting input node, an output node, a floating node, a first MOS input transistor, having its gate connected to said non-inverting input node, a second MOS input transistor, having its gate connected to said floating node, and its source connected to the source of said first MOS input transistor, current source means for supplying a bias current to the source of said first and second MOS input transistors, current mirror means, connected to the drains of said first and second MOS N-channel input transistors, for developing an output voltage proportionate to the difference between currents flowing in the drains of said first and second MOS input transistors, a first capacitor having a first electrode connected to said inverting input node and a second electrode connected to said floating node, a second capacitor having a first electrode connected to said output node and a second electrode connected to said floating node, an opaque layer covering portions of the surface of said integrated circuit containing active circuits, said opaque layer having an aperture therein above said second capacitor for allowing ultraviolet light to fall onto said first and second electrodes of said second capacitor whereby the offset voltage of said amplifier can be adapted while a source of ultraviolet light is present.

Claim 11

The amplifier of claim 6, further including means for selectively connecting together said inverting input and said non-inverting input.

Claim 12

The amplifier of claim 6 further including a pass gate having a first input connected to said inverting input node, a second input connected to said non-inverting input node, and a pass input.

Claim 13

An analog MOS inverting amplifier fabricated as a part of an integrated circuit, said amplifier having a gain of magnitude much larger than 1, including: an input node, an output node, an MOS N-channel transistor and an MOS P-channel transistor, said MOS N-channel transistor having a source connected to a source of negative voltage, and its drain connected to the drain of said MOS P-channel transistor and to said output node, the source of said MOS P-channel transistor connected to a source of positive voltage, a floating gate common to said MOS N-channel transistor and said MOS P-channel transistor, a first MOS capacitor having a first electrode connected to said node and a second electrode comprising a portion of said floating gate, a second MOS capacitor having a first electrode connected to said output node and a second electrode comprising a portion of said floating gate, an opaque layer covering portions of the surface of said integrated circuit containing active circuits, said opaque layer having an aperture therein above said second capacitor allowing for ultraviolet light to fall onto to said first and second electrodes of said second capacitor whereby the outset voltage of said amplifier can be adapted while a source of ultraviolet light is present.

Claim 14

An analog MOS inverting amplifier fabricated as a part of an integrated circuit, said amplifier having a gain of magnitude much larger than 1, including: an input node, an output node, an MOS N-channel transistor and an MOS P-channel transistor, said MOS N-channel transistor having a source connected to a source of negative voltage, and its drain connected to the drain of said MOS P-channel transistor and to said output node, the source of said MOS P-channel transistor connected to a source of positive voltage, a floating gate common to said MOS N-channel transistor and said MOS P-channel transistor, a first MOS capacitor having a first electrode connected to said node and a second electrode comprising a portion of said floating gate, a second MOS capacitor having a first electrode connected to said output node and a second electrode comprising a portion of said floating gate, an opaque layer covering portions of the surface of said integrated circuit containing active circuits, said opaque layer having an aperture therein above said second capacitor allowing for ultraviolet light to fall onto to said first and second electrodes of said second capacitor whereby the outset voltage of said amplifier can be adapted while a source of ultraviolet light is present.

Claim 15

A circuit, integrated on an integrated circuit, including: an input node, an output node, a floating node, a first MOS analog transconductance amplifier having an inverting input connected to a source of input reference voltage, a non-inverting input connected to said input connected to a source of bias voltage, a second MOS analog transconductance amplifier having an inverting input connected to said floating node, a noninverting input connected to a source of output reference voltage, an output connected to the noninverting input of said first MOS analog transconductance amplifier and a bias input connected to a source of bias voltage, a first MOS capacitor having a first electrode connected to said output node and a second electrode connected to the inverting input of said second MOS analog transconductance amplifier, a second MOS capacitor having a first electrode connected to the inverting input of said second MOS analog transconductance amplifier, and a second electrode connected to the non-inverting input of said second MOS analog transconductance amplifier, a third MOS capacitor having a first electrode connected to the inverting input of said second MOS analog transconductance amplifier, and a second electrode connected to a source of fixed voltage, a fourth MOS capacitor having a first electrode connected to the inverting input of said second MOS analog transconductance amplifier, and a second electrode connected to the output of said second MOS analog transconductance amplifier, and an opaque layer covering portions of the surface of said integrated circuit containing active circuits, said opaque layer having an aperture therein above said fourth capacitor for allowing ultraviolet light to fall onto said first and second electrodes of said fourth capacitor.

Claim 16

A circuit, integrated on an integrated circuit, including: an input node, an output node, a floating node, a first MOS analog transconductance amplifier having an inverting input connected to a source of input reference voltage, a non-inverting input connected to said input connected to a source of bias voltage, a second MOS analog transconductance amplifier having an inverting input connected to said floating node, a noninverting input connected to a source of output reference voltage, an output connected to the noninverting input of said first MOS analog transconductance amplifier and a bias input connected to a source of bias voltage, a first MOS capacitor having a first electrode connected to said output node and a second electrode connected to the inverting input of said second MOS analog transconductance amplifier, a second MOS capacitor having a first electrode connected to the inverting input of said second MOS analog transconductance amplifier, and a second electrode connected to the non-inverting input of said second MOS analog transconductance amplifier, a third MOS capacitor having a first electrode connected to the inverting input of said second MOS analog transconductance amplifier, and a second electrode connected to a source of fixed voltage, a fourth MOS capacitor having a first electrode connected to the inverting input of said second MOS analog transconductance amplifier, and a second electrode connected to the output of said second MOS analog transconductance amplifier, and an opaque layer covering portions of the surface of said integrated circuit containing active circuits, said opaque layer having an aperture therein above said fourth capacitor for allowing ultraviolet light to fall onto said first and second electrodes of said fourth capacitor.

Claim 17

The circuit of claim 10 wherein said fixed voltage is ground.

Claim 18

The circuit of claim 10, further including means for selectively connecting together said inverting input and said non-inverting input of said second MOS analog transconductance amplifier.

Claim 19

The amplifier of claim 10 further including a pass gate having a first node connected to said inverting input of said second MOS analog transconductance amplifier, a second node connected to said non-inverting input of said second MOS analog transconductance amplifier, and a pass input.

Claim 20

An analog MOS inverting amplifier fabricated as a part of an integrated circuit, said amplifier having a gain of magnitude much larger than 1, including: a non-inverting input node, an inverting input node, an output node, a floating node, a first MOS N-channel input transistor, having its gate connected to said non-inverting input node, a second MOS N-channel input transistor, having its gate connected to said floating node, a first current mirror including first and second MOS P-channel transistors, said first MOS P-channel transistor having its drain and gate connected to the drain of said first MOS N-channel input transistor and its source connected to a source of positive voltage, said second MOS P-channel transistor having its gate connected to the gate of said first MOS P-channel transistor, its drain connected to said output node and its source connected to said source of positive voltage, an MOS N-channel bias transistor having its gate connected to a source of bias voltage, its drain connected to the source of said first MOS N-channel input transistor, and its source connected to a source of negative voltage, a second current mirror including third and fourth MOS P-channel transistors, said third MOS P-channel transistor having its drain and gate connected to the drain of said second MOS N-channel input transistor and its source connected to a source of positive voltage, said fourth MOS P-channel transistor having its gate connected to the gate of said third MOS P-channel transistor and its source connected to said source of positive voltage, a third current mirror including first and second MOS N-channel current mirror transistors, said first MOS N-channel current mirror transistor having its drain and gate connected to the drain of said fourth MOS P-channel transistor, and its source connected to said source of negative voltage, said second MOS N-channel current mirror transistor having its gate connected to the gate of said first MOS N-channel current mirror transistor, its drain connected to said output node and its source connected to said source of negative voltage, a first MOS capacitor having a first electrode connected to said inverting input node and a second electrode connected to said floating node, a second MOS capacitor having a first electrode connected to said output node and a second electrode connected to said floating node, an opaque layer covering portions of the surface of said integrated circuit containing active circuits, said opaque layer having an aperture therein above said second capacitor for allowing ultraviolet light to fall onto said first and second electrodes of said second capacitor whereby the offset voltage of said amplifier can be adapted while a source of ultraviolet light is present.

Claim 21

An analog MOS inverting amplifier fabricated as a part of an integrated circuit, said amplifier having a gain of magnitude much larger than 1, including: a non-inverting input node, an inverting input node, an output node, a floating node, a first MOS N-channel input transistor, having its gate connected to said non-inverting input node, a second MOS N-channel input transistor, having its gate connected to said floating node, a first current mirror including first and second MOS P-channel transistors, said first MOS P-channel transistor having its drain and gate connected to the drain of said first MOS N-channel input transistor and its source connected to a source of positive voltage, said second MOS P-channel transistor having its gate connected to the gate of said first MOS P-channel transistor, its drain connected to said output node and its source connected to said source of positive voltage, an MOS N-channel bias transistor having its gate connected to a source of bias voltage, its drain connected to the source of said first MOS N-channel input transistor, and its source connected to a source of negative voltage, a second current mirror including third and fourth MOS P-channel transistors, said third MOS P-channel transistor having its drain and gate connected to the drain of said second MOS N-channel input transistor and its source connected to a source of positive voltage, said fourth MOS P-channel transistor having its gate connected to the gate of said third MOS P-channel transistor and its source connected to said source of positive voltage, a third current mirror including first and second MOS N-channel current mirror transistors, said first MOS N-channel current mirror transistor having its drain and gate connected to the drain of said fourth MOS P-channel transistor, and its source connected to said source of negative voltage, said second MOS N-channel current mirror transistor having its gate connected to the gate of said first MOS N-channel current mirror transistor, its drain connected to said output node and its source connected to said source of negative voltage, a first MOS capacitor having a first electrode connected to said inverting input node and a second electrode connected to said floating node, a second MOS capacitor having a first electrode connected to said output node and a second electrode connected to said floating node, an opaque layer covering portions of the surface of said integrated circuit containing active circuits, said opaque layer having an aperture therein above said second capacitor for allowing ultraviolet light to fall onto said first and second electrodes of said second capacitor whereby the offset voltage of said amplifier can be adapted while a source of ultraviolet light is present.

Claim 22

The amplifier of claim 14, further including means for selectively connecting together said input node and said non-inverting input node.

Claim 23

The amplifier of claim 14 further including a pass gate having a first input connected to said inverting input node, a second input connected to said non-inverting input node, and a pass input.

Claim 24

An analog MOS inverting amplifier fabricated as a part of an integrated circuit, said amplifier having a gain of magnitude much larger than 1, including: a non-inverting input node, an inverting input node, an output node, a floating node, a first MOS N-channel input transistor, having its gate connected to said non-inverting input node, a second MOS N-channel input transistor, having its gate connected to said floating node, an MOS N-channel bias transistor having its gate connected to a source of bias voltage, its drain connected to the source of said first MOS N-channel input transistor, and its source connected to a source of negative voltage, first and second MOS P-channel transistors, said first MOS P-channel transistor having its drain and gate connected to the drain of said first MOS N-channel input transistor and its source connected to a source of positive voltage, said second MOS P-channel transistor having its drain connected to the drain of said second MOS N-channel input transistor and its source connected to said source of positive voltage, a first MOS capacitor having a first electrode connected to said inverting input node and a second electrode connected to said floating node, a second MOS capacitor having a first electrode connected to said output node and a second electrode connected to said floating node, an opaque layer covering portions of the surface of said integrated circuit containing active circuits, said opaque layer having an aperture therein above said second capacitor for allowing ultraviolet light to fall onto said first and second electrodes of said second capacitor whereby the offset voltage of said amplifier can be adapted while a source of ultraviolet light is present.

Claim 25

An analog MOS inverting amplifier fabricated as a part of an integrated circuit, said amplifier having a gain of magnitude much larger than 1, including: a non-inverting input node, an inverting input node, an output node, a floating node, a first MOS N-channel input transistor, having its gate connected to said non-inverting input node, a second MOS N-channel input transistor, having its gate connected to said floating node, an MOS N-channel bias transistor having its gate connected to a source of bias voltage, its drain connected to the source of said first MOS N-channel input transistor, and its source connected to a source of negative voltage, first and second MOS P-channel transistors, said first MOS P-channel transistor having its drain and gate connected to the drain of said first MOS N-channel input transistor and its source connected to a source of positive voltage, said second MOS P-channel transistor having its drain connected to the drain of said second MOS N-channel input transistor and its source connected to said source of positive voltage, a first MOS capacitor having a first electrode connected to said inverting input node and a second electrode connected to said floating node, a second MOS capacitor having a first electrode connected to said output node and a second electrode connected to said floating node, an opaque layer covering portions of the surface of said integrated circuit containing active circuits, said opaque layer having an aperture therein above said second capacitor for allowing ultraviolet light to fall onto said first and second electrodes of said second capacitor whereby the offset voltage of said amplifier can be adapted while a source of ultraviolet light is present.

Claim 26

The amplifier of claim 17, further including means for selectively connecting together said input node and said non-inverting input node.

Claim 27

The amplifier of claim 17 further including a pass gate having a first input connected to said inverting input node, a second input connected to said non-inverting input node, and a pass input.