Patent US4935647A successfully refreshed from Google Patents.
US4935647A
Expired / Lapsed
US
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Group III - V semiconductor devices with improved switching speeds
Assignee: Microsemi Communications Inc
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Filing: 1988-10-19
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Granted: 1990-06-19
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Expires: 2008-10-19
Abstract
Abstract To decrease the time required to charge parasitic capacitances, and to thereby increase the maximum permissible switching frequency to which a logic circuit can respond, a GaAs device is disclosed having a current-injecting circuit that generates an initial pulse of capacitor-charging current during a "0"-to-"1" transition in the output state of a GaAs device. The pulse is sufficiently large to quickly charge the parasitic capacitances, and of sufficiently brief duration so that a minimum line width is permissible which is substantially equivalent to that which would be applicable in the absence of the current-injecting circuit.
Inventors
- 👤 William Larkins
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 20:46
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/08; H03K19/094; H03K19/0952
Claims Analysis
Total Claims: 3
Claim 1
Independent Claim
254 words
A solid state inverter comprising: first and second power bus means; a first depletion mode GaAs transistor having a pair of main terminal means and a gate terminal means electrically coupled to one of its main terminal means at a first node to form an first active impedance element; the other of the main terminal means being coupled to the first power bus means; a first enhancement mode GaAs transistor having one of a pair of main terminal means respectively electrically coupled to the first node and the other of the pair of main terminal means electrically coupled to the second power bus means, the first enhancement mode GaAs transistor further having gate terminal means available to receive an input logic level signal to the inverter; a second depletion mode GaAs transistor having one of a pair of main terminal means electrically coupled to the first bus means, a second enhancement-mode GaAs transistor having one of a pair of main terminal means electrically coupled to the second bus means and the other of the pair of main terminal means electrically coupled to the other main terminal of the second depletion mode GaAs transistor to define an inverter output terminal; GaAs diode means having cathode terminal means electrically coupled to the first node and further having anode terminal means; and a third enhancement-mode GaAs transistor having gate terminal means coupled to the second node, and a pair of main terminal means respectively electrically coupled to the anode terminal means and the second power bus means.
Claim 2
Dependent Claim
254 words
A solid state inverter comprising: first and second power bus means; a first depletion mode GaAs transistor having a pair of main terminal means and a gate terminal means electrically coupled to one of its main terminal means at a first node to form an first active impedance element; the other of the main terminal means being coupled to the first power bus means; a first enhancement mode GaAs transistor having one of a pair of main terminal means respectively electrically coupled to the first node and the other of the pair of main terminal means electrically coupled to the second power bus means, the first enhancement mode GaAs transistor further having gate terminal means available to receive an input logic level signal to the inverter; a second depletion mode GaAs transistor having one of a pair of main terminal means electrically coupled to the first bus means, a second enhancement-mode GaAs transistor having one of a pair of main terminal means electrically coupled to the second bus means and the other of the pair of main terminal means electrically coupled to the other main terminal of the second depletion mode GaAs transistor to define an inverter output terminal; GaAs diode means having cathode terminal means electrically coupled to the first node and further having anode terminal means; and a third enhancement-mode GaAs transistor having gate terminal means coupled to the second node, and a pair of main terminal means respectively electrically coupled to the anode terminal means and the second power bus means.
Claim 3
Dependent Claim
21 words
The inverter of claim 1 wherein the diode means is a Schottky diode inherent in the structure of a GaAs transistor.
References Cited (Backward Citations)
EP0256918A1
Cited
US4810969A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-06-18 | 1993-12-18 | 1994-06-19 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-06-18 | 1997-12-18 | 1998-06-19 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-06-18 | 2001-12-18 | 2002-06-19 | $7700.00 | Window Closed / Lapsed |