n-Dimensional modular multiprocessor lattice architecture

Claim 1

A multiprocessor system having a plurality of n-dimensional processing element (FE) modular entities (12,210) interconnected in an n-dimensional lattice architecture, where n is a non-zero integer, in which a plurality of said PE modular entities each comprises: a signal processing core (24); a CPU RAM (310); a program Memory (312); an interrupt controller (302); at least one dual port random access memory (DPR: 34,38; 212,222,232); and least one a single CPU data/address bus (32) having at external port (44,48) and interconnecting said signal processing core, said CPU RAM, said program memory, said interrupt controller, said DPR and said external port with each other; and in which the single CPU data/address bus in a first one of said PE modular entities is connected by one of its ports to a DPR of a second one of said PE modular entities for pairwise interchange of data and address signals between said first and second PE modular entities, one DPR of said first PE modular entity is connected to a port of the single data/address bus of a third one of said PE modular entities for pairwise interchange of data and address signals between said first and third PE modular entities, and the single CPU data/address bus of said second PE modular entity is connected by one of its ports to a DPR of a fourth one of said PE modular entities for pairwise interchange of data and address signals between said second and fourth PE modular entities.