Patent US4933734A successfully refreshed from Google Patents.
US4933734A
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Semiconductor device having field effect transistors and manufacturing method therefor
Assignee: Mitsubishi Electric Corp
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Filing: 1988-12-05
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Granted: 1990-06-12
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Expires: 2008-12-05
Abstract
Abstract A channel surface with a channel region and a gate electrode opposing to each other is formed approximately vertical to a main surface of a semiconductor substrate in the field effect transistor (FET). A p type (n type) single crystal silicon layer is formed in a hole of an insulating layer on the main surface of the substrate. N type (p type) drain and source regions are formed defining the channel region in the single crystal silicon layer. A gate electrode is formed above the channel region on the side wall of the single crystal silicon layer in the hole. The area of the main surface of the substrate occupied by one FET can be reduced in this manner. A semiconductor device can be provided in which FETs are integrated to a higher degree without degrading performance of the transistors. The method for manufacturing the semiconductor device comprises the steps of forming an insulating layer with a hole reaching to the main surface of the substrate, forming a single crystal silicon layer in the hole, forming a gate electrode on the side wall surface of the single crystal silicon layer, and forming source and drain regions in the single crystal silicon layer in selfalignment.
Inventors
- 👤 Yasuo Inoue
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 06:57
CPC Classifications
H; H10; H10D; H10D62/00; H10D62/10; H10D62/13; H10D62/149; H10D62/151; H10D30/00; H10D30/01; H10D30/021; H10D30/026; H10D30/027; H10D30/0275; H10D30/60; H10D64/00; H10D64/01; H10D64/025; H10D64/027; H10D84/00; H10D84/01; H10D84/0123; H10D84/0126; H10D84/0165; H10D84/02; H10D84/03; H10D84/038; H10D84/90; H10D84/903; H10D84/907; H10D84/80; H10D84/82; H10D84/83; H10D84/85; H10D84/859
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
324 words
A semiconductor device having a field effect transistor of a first conductivity type and a field effect transistor of a second conductivity type, comprising: a semiconductor substrate having a main surface; an insulating layer formed on the main surface of said semiconductor substrate, having a hole whose bottom surface being a portion of the main surface, which is exposed, of said semiconductor substrate; a first single crystal semiconductor layer of the first conductivity type formed in the hole of said insulating layer on the bottom surface and at least on one side wall surface of the hole of said insulating layer; first and second impurity regions of the second conductivity type formed spaced apart from each other in a region of said first single crystal semiconductor layer, said first and second impurity regions defining a first channel region in said first single crystal semiconductor layer; a first gate electrode formed in said hole above said first channel region on the side wall surface of said first single crystal semiconductor layer with an insulating layer interposed therebetween, said electrode being insulated from a portion of the exposed main surface of said semiconductor substrate; a second single crystal semiconductor layer of the second conductivity type formed in the hole of said insulating layer on the bottom surface and at least on the other side wall surface of the hole of said insulating layer; third and fourth impurity regions of the first conductivity type formed spaced apart from each other in a region of said second single crystal semiconductor layer, said third and fourth impurity regions defining a second channel region in said second single crystal semiconductor layer; and a second gate electrode formed in said hole above said second channel region on the side wall surface of said second single crystal semiconductor layer with a gate insulating layer interposed therebetween, said electrode being insulated from a portion of the exposed main surface of said semiconductor substrate.
Claim 2
Dependent Claim
324 words
A semiconductor device having a field effect transistor of a first conductivity type and a field effect transistor of a second conductivity type, comprising: a semiconductor substrate having a main surface; an insulating layer formed on the main surface of said semiconductor substrate, having a hole whose bottom surface being a portion of the main surface, which is exposed, of said semiconductor substrate; a first single crystal semiconductor layer of the first conductivity type formed in the hole of said insulating layer on the bottom surface and at least on one side wall surface of the hole of said insulating layer; first and second impurity regions of the second conductivity type formed spaced apart from each other in a region of said first single crystal semiconductor layer, said first and second impurity regions defining a first channel region in said first single crystal semiconductor layer; a first gate electrode formed in said hole above said first channel region on the side wall surface of said first single crystal semiconductor layer with an insulating layer interposed therebetween, said electrode being insulated from a portion of the exposed main surface of said semiconductor substrate; a second single crystal semiconductor layer of the second conductivity type formed in the hole of said insulating layer on the bottom surface and at least on the other side wall surface of the hole of said insulating layer; third and fourth impurity regions of the first conductivity type formed spaced apart from each other in a region of said second single crystal semiconductor layer, said third and fourth impurity regions defining a second channel region in said second single crystal semiconductor layer; and a second gate electrode formed in said hole above said second channel region on the side wall surface of said second single crystal semiconductor layer with a gate insulating layer interposed therebetween, said electrode being insulated from a portion of the exposed main surface of said semiconductor substrate.
Claim 3
Dependent Claim
37 words
A semiconductor device having field effect transistors according to claim 1, wherein said first gate electrode and said second gate electrode comprise a common gate electrode in which the first and second gate electrodes are formed integrally.
Claim 4
Dependent Claim
183 words
A semiconductor device having field effect transistors according to claim 1, wherein a horizontal shape of the hole of said insulating layer is approximately rectangular: said first single crystal semiconductor layer is formed along one side wall surface of said hole, whose horizontal shape being approximately rectangular with one side opened, said first region being formed at the center and said first and second impurity regions formed at opposing end portions of the rectangular shape with one side opened: said second single crystal semiconductor layer is formed along the other side wall surface of said hole opposing to said first single crystal semiconductor layer, whose horizontal shape being approximately rectangular with one side opened, said second channel region formed at the center and said third and fourth impurity regions formed at opposing end portions of the rectangular shape with one side opened; and said first gate electrode and said second gate electrode comprise a conductive layer formed in a region surrounded by said first single crystal semiconductor layer and said second single crystal semiconductor layer being insulated therefrom and buried in said hole.
Claim 5
Dependent Claim
71 words
A semiconductor device having field effect transistors according to claim 2, wherein said common gate electrode comprises an electrode portion formed on said first and second channel regions with a gate insulating layer interposed therebetween, and a contact portion formed extending from the electrode portion over upper surfaces of said first and second crystal semiconductor layers with an insulating layer interposed therebetween, having a surface electrically connected to a wiring layer.
References Cited (Backward Citations)
US4400411A
Cited
WO1986003341A1
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 1993-06-11 | 1993-12-11 | 1994-06-12 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-06-11 | 1997-12-11 | 1998-06-12 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-06-11 | 2001-12-11 | 2002-06-12 | $7700.00 | Window Closed / Lapsed |