Method and apparatus for monitoring peripheral device communications

Claim 1

In a digital data processor having a first input/output controller for communicating with one or more peripheral devices over a common peripheral device bus, the improvement wherein A. said peripheral device bus includes first and second input/output buses for transferring information-representative signals, including at least one of a data, address and control signal, between said first input/output controller and said peripheral devices, B. said first input/output controller includes first and second processing sections, each said section being coupled with said first and second input/output buses for communication with said peripheral devices, each of said first and second processing sections being responsive to duplicate signals received substantially synchronously and simultaneously with the other processing section to produce, in the absence of fault, identical resultant information-representative signals synchronously and simultaneously therewith, C. first bus interface means coupled with said first input/output controller and with said peripheral bus for transferring said information-representative signals between each of said first and second input/output buses and each of said first and second processing sections, D. a second input/output controller coupled with said peripheral device bus for duplicating at least some of the operations of said first input/output controlling, E. second bus interface means coupled with second input/output controller and with said peripheral bus for transferring said information-representative signals between said first and second input/output buses and said second input/output controller, F. flash circuitry means coupled to said first and second bus interface means for monitoring information-representative signals transferred on said first and second input/output buses and for generating a set of one or more status signals indicative of the synchronous transfer of at least selected identical ones of said information-representative signals on each of said first and second input/output buses, said status signals including one or more timing signals, said flash circuitry means including means for applying said timing signals synchronously and simultaneously to said first and second bus interface means for transfer to said peripheral devices and said input/output controllers, and G. at least said first input/output controller and said peripheral devices including means for responding to said timing signals for processing information-representative signals transferred to them on said first and second input/output buses.