Vertical MOSFET having voltage regulator diode at shallower subsurface position

Claim 1

A vertical MOSFET device, comprising: a first substrate layer of a first conductivity type formed in a semiconductor substrate and including a first major surface of the substrate; an insulated gate electrode formed above said first surface of said substrate; a gate insulating layer insulating the gate electrode from the substrate; a source region of said first conductivity type extending into the substrate from said first surface; a channel region of second conductivity type formed in said first substrate layer so as to surround said source region and separate said source region from said first substrate layer, said channel region comprising a deep subregion formed under said insulating gate electrode so that a conducting channel can be induced in said deep subregion immediately below said gate electrode, between said source region and said first substrate layer, and a shallow region surrounded by said deep subregion and shallower from said first surface than said deep subregion; and a highly doped underlying layer of said first conductivity type formed under said shallow subregion in contact with said shallow subregion so as to form a p-n junction between said underlying layer and said shallow subregion for preventing a potential of said first substrate layer from exceeding a predetermined value, said p-n junction being formed at a position shallower from said first surface than said deep subregion; wherein, the impurity concentration of said shallow subregion is higher than that of said deep subregion and the impurity concentration of said underlying layer is higher than that of said first substrate layer.