ECL-to-TTL translator circuit with ground bounce protection

Claim 2

An ECL-to-TTL translator circuit for converting ECL logic level signals to TTL logic level signals, said translator circuit comprising: ECL circuit means (112) for receiving true and complementary data input signals having ECL logic levels and for generating input signals; input stage means (114) responsive to said input signals for generating first and second control signals; TTL output stage means (116) responsive to said control signals for generating at an output terminal an output signal which is TTL compatible, said output stage means including an upper TTL output transistor (Q8) and a lower TTL output transistor (Q7), said upper output transistor having its collector coupled to a TTL power supply potential via a current-limiting resistor (R7), its base coupled to receive said first control signal, and its emitter connected to said output terminal, said lower output transistor having its collector connected to said output terminal, its base coupled to receive said second control signal and its emitter connected to a TTL ground potential; ground bounce protection circuit means (124) coupled to said lower output transistor for maintaining said lower output transistor in its turned-off condition when said ground potential is being pulled down due to the switching of said output terminal between a low logic level and a high logic level; and said ground bounce protection circuit means (124) including a voltage-independent current source, a reference resistor (R15), and a switching transistor (Q15), said current source being coupled between said TTL power supply potential and one end of said reference resistor (R15) to provide a reference voltage, the other end of said resistor (R15) being connected to an ECL ground potential, said switching transistor (Q15) having its collector connected to the base of said lower output transistor (Q7), its base connected to said one end of said reference resistor (R15), and its emitter connected to said TTL ground potential.

Claim 3

A translator circuit as claimed in claim 1, wherein said current source includes first and second transistors (Q16, Q17) and first and second resistors (R17, R16), said first transistor (Q16) having its collector connected to said TTL power supply potential, its base coupled to said TTL power supply potential via said first resistor (R17), and its emitter connected to the base of said second transistor (Q17), said second transistor (Q17) having its collector connected to the base of said first transistor (Q16) and its emitter coupled to the emitter of said first transistor (Q16) via said second resistor (R16).

Claim 4

A translator circuit as claimed in claim 1, further comprising speed-up circuit means (126) for limiting voltage swings at the output of said input stage means (114) so as to increase its switching speed.

Claim 5

A translator circuit as claimed in claim 3, wherein said speed-up circuit means (126) includes first and second speed-up transistors (Q14, Q5), first and second resistors (R4, RB), and first, second and third diodes (D6, D7, D8) for setting threshold voltages at the bases of said first and second speed-up transistors (Q14, Q5) at 3V SCH -V BE (Q14) and 2V SCH -V BE (Q5), respectively.

Claim 6

A translator circuit as claimed in claim 3, further comprising active pull-down circuit means (120) responsive to said input signals for facilitating turning off said lower output transistor (Q7) when the output terminal is switching from the low logic level to the high logic level.

Claim 7

A translator circuit as claimed in claim 1, further comprising active pull-down circuit means (120) responsive to said input signals for facilitating turning off said lower output transistor (Q7) when the output terminal is switching from the low logic level to the high logic level.

Claim 8

A translator circuit as claimed in claim 5, wherein said active pull-down circuit means (120) includes a cut-off transistor (Q13), first and second resistors (R6, R14), and first and second diodes (D3, D4), said out-off transistor (Q13) having its collector coupled to said TTL power supply potential via said first resistor (R14), its base coupled to said TTL power supply potential via said first diode (D3) and said second resistor (R6), and its emitter connected to said TTL ground potential, said second diode (D4) being coupled between said first diode (D3) and the collector of said out-off transistor (Q13), the collector of said out-off transistor (Q13) being further connected to the base of said lower output transistor (Q7).

Claim 9

A translator circuit as claimed in claim 1, further comprising clamping means (122) coupled to said upper output transistor (Q8) for clamping the high voltage level at the output terminal to a fixed upper voltage so as to increase its switching speed.

Claim 10

A translator circuit as claimed in claim 6, further comprising clamping means (122) coupled to said upper output transistor (Q8) for clamping the high voltage level at the output terminal to a fixed upper vantage so as to increase its switching speed.

Claim 11

A transactor circuit as claimed in claim 8, wherein in said clamping means (122) includes a clamping resistor (R9) and a plurality of series-connected diodes (D9-D15) coupled between the base of said upper output transistor (Q8) and said TTL ground potential, said clamping resistor (R9) being coupled between said TTL power supply potential and the junction of the cathode of a first diode of said plurality of series-connected diodes (D9-D15) and the anode of a second diode of said plurality of series-connected diodes, the anode of said first diode being coupled to the base of said upper output transistor (Q8).

Claim 12

A translator circuit as claimed in claim 1, further comprising enable gate means (118) coupled to said output stage means (116) for selectively disabling both said upper and lower output transistors (Q8, Q7) so as to provide a high impedance third level at said output terminal.

Claim 13

An ECL-to-TTL translator circuit for converting ECL logic level signals to TTL logic level signals, said translator circuit comprising: ECL circuit means (112) for receiving true and complementary date input signals having ECL logic levels and for generating input signals; input stage means (114) responsive to said input signals for generating first and second control signals; TTL output stage means (116) responsive to said control signals for generating at an output terminal an output signal which is TTL compatible, said output stage means including an upper TTL output transistor (Q8) and a lower TTL output transistor (Q7), said upper output transistor having its collector coupled to a TTL power supply potential via a current-limiting resistor (R7), its base coupled to receive said first control signal, and its emitter connected to said output terminal, said lower output transistor having its collector connected to said output terminal, its base coupled to receive said second control signal and its emitter connected to a TTL ground potential; speed-up circuit means (126) for limiting voltage swings at the output of said input stage means (114) so as to increase its switching speed; active pull-down means (120) responsive to said input signals for facilitating turning off said lower output transistor (Q7) when the output terminal is switching from a low logic level to a high logic level; clamping means (122) coupled to said upper output transistor (Q8) for clamping the high logic level at the output terminal to a fixed upper voltage so as to increase its switching speed; ground bounce protection circuit means (124) coupled to said lower output transistor for maintaining said lower output transistor in its turned-off condition when said ground potential is being pulled down due to the switching of said output terminal between the low logic level and the high logic level; and enable gate means (118) coupled to said output stage means (116) for selectively disabling both said upper and lower output transistors (Q8, Q7) so as to provide a high impedance third level at said output terminal.

Claim 14

An ECL-to-TTL translator circuit for converting ECL logic level signals to TTL logic level signals, said translator circuit comprising: ECL circuit means (112) for receiving true and complementary date input signals having ECL logic levels and for generating input signals; input stage means (114) responsive to said input signals for generating first and second control signals; TTL output stage means (116) responsive to said control signals for generating at an output terminal an output signal which is TTL compatible, said output stage means including an upper TTL output transistor (Q8) and a lower TTL output transistor (Q7), said upper output transistor having its collector coupled to a TTL power supply potential via a current-limiting resistor (R7), its base coupled to receive said first control signal, and its emitter connected to said output terminal, said lower output transistor having its collector connected to said output terminal, its base coupled to receive said second control signal and its emitter connected to a TTL ground potential; speed-up circuit means (126) for limiting voltage swings at the output of said input stage means (114) so as to increase its switching speed; active pull-down means (120) responsive to said input signals for facilitating turning off said lower output transistor (Q7) when the output terminal is switching from a low logic level to a high logic level; clamping means (122) coupled to said upper output transistor (Q8) for clamping the high logic level at the output terminal to a fixed upper voltage so as to increase its switching speed; ground bounce protection circuit means (124) coupled to said lower output transistor for maintaining said lower output transistor in its turned-off condition when said ground potential is being pulled down due to the switching of said output terminal between the low logic level and the high logic level; and enable gate means (118) coupled to said output stage means (116) for selectively disabling both said upper and lower output transistors (Q8, Q7) so as to provide a high impedance third level at said output terminal.

Claim 15

A translator circuit as claimed in claim 12, wherein said speed-up circuit means (126) includes first and second speed-up transistors (Q14, Q5), first and second resistors (R4, R8), and first, second and third diodes (D6, D7, D8) for setting threshold voltages at the bases of said first and second speed-up transistors (Q14, Q5) at 3V SCH -V BE (Q14) and 2V SCH -V BE (Q5), respectively.

Claim 16

A translator circuit as claimed in claim 12, wherein said active pull-down circuit means (120) includes a cut-off transistor (Q13), first and second resistors (R6, R14), and first and second diodes (D3, D4), said cut-off transistor (Q13) having its collector coupled to said TTL power supply potential via said first resistor R14), its base coupled to said TTL power supply potential via said first diode (D3) and said second resistor (R6), and its emitter connected to said TTL ground potential, said second diode (D4) being coupled between said first diode (D3) and the collector of said out-off transistor (Q13), the collector of said cut-off transistor (Q13) being further connected to the base of said lower output transistor (Q7).

Claim 17

A translator circuit as claimed in claim 12, wherein in said clamping means (122) includes a clamping resistor (R9) and a plurality of series-connected diodes (D9-D15) coupled between the base of said upper output transistor (Q8) and said TTL ground potential, said clamping resistor (R9) being coupled between said TTL power supply potential and the junction of the cathode of a first diode of said plurality of series-connected diodes (D9-D15) and the anode of a second diode of said plurality of series-connected diodes, the anode of said first diode being coupled to the base oF said upper output transistor (Q8).

Claim 18

An ECL-to-TTL translator circuit for converting ECL logic level signals to TTL logic level signals, said translator circuit comprising: TTL output stage means (116) responsive to control signals for generating at an output terminal an output signal which is TTL compatible, said output stage means including an upper TTL output transistor (Q8) and a lower TTL output transistor (Q7), said upper output transistor having its collector coupled to a TTL power supply potential via a current-limiting resistor (R7), its base coupled to receive a first one of said control signals, and its emitter connected to said output terminal, said lower output transistor having its collector connected to said output terminal, its base coupled to receive a second one of said control signals and its emitter connected to a TTL ground potential; ground bounce protection circuit means (124) coupled to said lower output transistor for maintaining said lower output transistor in its turned-off condition when said ground potential is being pulled down due to the switching of said output terminal between a low logic level and a high logic level; and said ground bounce protection circuit means including a voltage-independent current source, a reference resistor (R15), and a switching transistor (Q15), said current source being coupled between said TTL power supply potential and one end of said reference resistor (R15) to provide a reference voltage, the other end of said resistor (R15) being connected to an ECL ground potential, said switching transistor (Q15) having its collector connected to the base of said lower output transistor (Q7), its base connected to said one end of said reference resistor (R15), and its emitter connected to said TTL ground potential.

Claim 19

An ECL-to-TTL translator circuit for converting ECL logic level signals to TTL logic level signals, said translator circuit comprising: TTL output stage means (116) responsive to control signals for generating at an output terminal an output signal which is TTL compatible, said output stage means including an upper TTL output transistor (Q8) and a lower TTL output transistor (Q7), said upper output transistor having its collector coupled to a TTL power supply potential via a current-limiting resistor (R7), its base coupled to receive a first one of said control signals, and its emitter connected to said output terminal, said lower output transistor having its collector connected to said output terminal, its base coupled to receive a second one of said control signals and its emitter connected to a TTL ground potential; ground bounce protection circuit means (124) coupled to said lower output transistor for maintaining said lower output transistor in its turned-off condition when said ground potential is being pulled down due to the switching of said output terminal between a low logic level and a high logic level; and said ground bounce protection circuit means including a voltage-independent current source, a reference resistor (R15), and a switching transistor (Q15), said current source being coupled between said TTL power supply potential and one end of said reference resistor (R15) to provide a reference voltage, the other end of said resistor (R15) being connected to an ECL ground potential, said switching transistor (Q15) having its collector connected to the base of said lower output transistor (Q7), its base connected to said one end of said reference resistor (R15), and its emitter connected to said TTL ground potential.

Claim 20

A translator circuit as claimed in claim 16, wherein said current source includes first and second transistors (Q16, Q17) and first and second resistors (R17, R16), said first transistor (Q16) having its collector connected to said TTL power supply potential, its base coupled to said TTL power supply potential via said first resistor (R17), and its emitter connected to the base of said second transistor (Q17), said second transistor (Q17) having its collector connected to the base of said first transistor (Q16) and its emitter coupled to the emitter of said first transistor (Q16) via said second resistor (R16).