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US4930098A
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Shift register programming for a programmable logic device
Assignee: Altera Corp
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Filing: 1988-12-30
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Granted: 1990-05-29
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Expires: 2008-12-30
Abstract
Abstract A programmable logic device in which memory cells are removed from the signal path. Input signals are coupled to an inverting and a non-inverting buffer to provide a complementary pair of outputs from the buffers. In one embodiment, a memory cell is provided to control enablement of each buffer and the output of each pair of complementary buffers is coupled together to provide an output. In another embodiment, the complementary pair of outputs from the buffer are inputted to a multiplexer wherein a single memory cell controls the selection of the signal or its complement to be outputted from the multiplexer. The memory cells are each coupled to its corresponding latch or shift register for latching a stored state of the memory cell. Shift registers provide for external programming to emulate stored memory cell states.
Inventors
- 👤 Michael J. Allen
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 03:37
CPC Classifications
G; G11; G11C; G11C7/00; G11C7/10; G11C7/1015; G11C7/1036; G11C7/1051; H; H03; H03K; H03K19/00; H03K19/02; H03K19/173; H03K19/177; H03K19/17704; H03K19/17708; H03K19/17712
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
134 words
In a programmable logic device (PLD) having a plurality of inputs and a plurality of outputs and a memory array for storing a program, an apparatus for operating on said inputs according to a stored program, comprising: a plurality of memory cells comprising said memory array for storing said program; a plurality of registers serially arranged, and wherein each register is coupled to its corresponding memory cell for latching a stored state of its memory cell; a plurality of buffers, wherein each of said buffers is coupled to receive a selective one of said inputs and, if enabled, provides a corresponding output; each said buffer also being coupled to its corresponding memory cell through its corresponding register such that enablement of said buffer is determined by said stored state of its corresponding memory cell.
Claim 2
Dependent Claim
134 words
In a programmable logic device (PLD) having a plurality of inputs and a plurality of outputs and a memory array for storing a program, an apparatus for operating on said inputs according to a stored program, comprising: a plurality of memory cells comprising said memory array for storing said program; a plurality of registers serially arranged, and wherein each register is coupled to its corresponding memory cell for latching a stored state of its memory cell; a plurality of buffers, wherein each of said buffers is coupled to receive a selective one of said inputs and, if enabled, provides a corresponding output; each said buffer also being coupled to its corresponding memory cell through its corresponding register such that enablement of said buffer is determined by said stored state of its corresponding memory cell.
Claim 3
Dependent Claim
33 words
The apparatus of claim 1 wherein each said buffer is comprised of an inverter and a non-inverter, such that one of said inverter and non-inverter is enabled by its buffer's corresponding memory cell.
Claim 4
Dependent Claim
31 words
The apparatus of claim 2 wherein said registers are shift registers coupled to receive external programming signals for enabling of said buffers without accessing said stored states of said memory cells.
Claim 5
Dependent Claim
17 words
The apparatus of claim 3 wherein said memory cells are comprised of an erasable programmable read-only-memory (EPROM).
Claim 6
Dependent Claim
153 words
A programmable logic device (PLD) having a plurality of inputs and a plurality of outputs and a memory array for storing a program wherein said outputs are determined by said program operating on said inputs, comprising: a plurality of memory cells for storing said program; a plurality of registers serially arranged, wherein each register is coupled to its corresponding memory cell for latching a stored state of its memory cell; a plurality of buffers for buffering said inputs, wherein each of said inputs is coupled to a pair of said buffers, said pair being an inverter and a non-inverter; a plurality of multiplexers (MUXs) each coupled to a corresponding pair of buffers to receive said input and its complement; each said MUX also being coupled to its corresponding memory cell through its corresponding register such that selection between its input and complement is determined by said stored state of said corresponding memory cell.
Claim 7
Dependent Claim
153 words
A programmable logic device (PLD) having a plurality of inputs and a plurality of outputs and a memory array for storing a program wherein said outputs are determined by said program operating on said inputs, comprising: a plurality of memory cells for storing said program; a plurality of registers serially arranged, wherein each register is coupled to its corresponding memory cell for latching a stored state of its memory cell; a plurality of buffers for buffering said inputs, wherein each of said inputs is coupled to a pair of said buffers, said pair being an inverter and a non-inverter; a plurality of multiplexers (MUXs) each coupled to a corresponding pair of buffers to receive said input and its complement; each said MUX also being coupled to its corresponding memory cell through its corresponding register such that selection between its input and complement is determined by said stored state of said corresponding memory cell.
Claim 8
Dependent Claim
32 words
The PLD of claim 5 wherein said registers are shift registers coupled to receive external programming signals for controlling selection of said MUXs without accessing said stored states of said memory cells.
Claim 9
Dependent Claim
17 words
The PLD of claim 6 wherein said memory cells are comprised of an erasable programmable read-only-memory (EPROM).
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-05-28 | 1993-11-27 | 1994-05-29 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-05-28 | 1997-11-27 | 1998-05-29 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-05-28 | 2001-11-27 | 2002-05-29 | $7700.00 | Window Closed / Lapsed |