US4929883A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Circuit for sensing the transistor current waveform
Assignee: STMicroelectronics SA
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Filing: 1989-09-13
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Granted: 1990-05-29
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Expires: 2009-09-13
Abstract
Abstract A circuit for sensing the waveform of the current in a transistor, including a first transistor which is controlled on its base by a switching signal; a second transistor which is controlled on its base by a control signal which is inverted and delayed with respect to the switching signal, the collector of the first transistor being connected through a diode to the collector of the second transistor, the emitter of the first transistor and the emitter of the second transistor being connected to the ground; a third transistor connected with its base to the collector of the second transistor and with its emitter to the ground through a resistor, the third transistor being switched on when the second transistor is switched off and the first transistor is on.
Inventors
- 👤 Davide Chieli
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 09:42
CPC Classifications
H; H03; H03K; H03K4/00; H03K4/06; H03K4/08; H03K4/48; H03K17/00; H03K17/08; H03K17/082; H03K17/0826
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
113 words
A circuit for sensing a transistor current waveform, including a switching transistor having collector and emitter terminals connected between a first and a second reference potential line, and a base terminal receiving a switching signal, and a transducing differential amplifier circuit connected at the input to said collector and emitter terminals of said switching transistor and generating at the output a transduced voltage proportional to the emitter to collector voltage of said switching transistor, said transduced voltage being fed to a sensing resistor arranged between the output of said transducing differential amplifier circuit and said second reference potential line and generating a sensing current proportional to the collector current of said switching transistor.
Claim 2
Dependent Claim
113 words
A circuit for sensing a transistor current waveform, including a switching transistor having collector and emitter terminals connected between a first and a second reference potential line, and a base terminal receiving a switching signal, and a transducing differential amplifier circuit connected at the input to said collector and emitter terminals of said switching transistor and generating at the output a transduced voltage proportional to the emitter to collector voltage of said switching transistor, said transduced voltage being fed to a sensing resistor arranged between the output of said transducing differential amplifier circuit and said second reference potential line and generating a sensing current proportional to the collector current of said switching transistor.
Claim 3
Dependent Claim
85 words
A circuit according to claim 1, wherein said transducing differential amplifier circuit comprises a transducing transistor having its collector terminal connected to a third reference potential line, its emitter terminal connected to said second reference potential line through said sensing resistor and its base terminal connected to a switch element receiving a control signal correlated to said switching signal, said transducing differential amplifier circuit further comprising a diode connected between said base terminal of said transducing transistor and said collector terminal of said switching transistor.
Claim 4
Dependent Claim
51 words
A circuit according to claim 2, wherein said switch element comprises a control transistor having its collector terminal connected to said base terminal of said transducing transistor, its emitter terminal connected to said second reference potential line and its base terminal receiving said control signal being opposed to said switching signal.
Claim 5
Dependent Claim
25 words
A circuit according to claim 3, wherein said control signal has a falling edge delayed with respect to a leading edge of said switching signal.
Claim 6
Dependent Claim
45 words
A circuit according to claim 3, comprising a delay means receiving said switching signal and generating a delayed signal and a NAND gate having a first input receiving said switching signal, a second input receiving said delayed signal and an output generating said control signal.
Claim 7
Dependent Claim
23 words
A circuit according to claim 5, wherein said delay means defines a delay time corresponding to the reaction time of the switching transistor.
Claim 8
Dependent Claim
25 words
A circuit according to claim 2, comprising a current source connected between said third reference potential line and said base terminal of said transducing transistor.
Claim 9
Dependent Claim
14 words
A circuit according to claim 1, wherein said switching transistor is a power transistor.
Claim 10
Dependent Claim
15 words
A circuit according to claim 1, wherein said second reference potential line is the ground.
References Cited (Backward Citations)
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-05-28 | 1993-11-27 | 1994-05-29 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-05-28 | 1997-11-27 | 1998-05-29 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-05-28 | 2001-11-27 | 2002-05-29 | $7700.00 | Window Closed / Lapsed |