Digital phase comparing circuit

Claim 2

A digital phase comparing circuit, comprising: first and second input terminals receiving first and second input signals, respectively; a first rise detecting circuit for detecting a rise of said first input signal and outputting a first detection signal; a second rise detecting circuit for detecting a rise of said second input signal and outputting a second detection signal; a first flip-flop, operatively connected to said first rise detecting circuit, being set in response to said first detection signal and being reset in response to a reset signal; a second flip-flop, operatively connected to said second rise detecting circuit, being set in response to said second detection signal and being reset in response to said reset signal; and a logical state circuit responsive to an output of said first flip-flop and an output of said second flip-flop and, when the outputs of said first and second flip-flops coincide with each other, outputting said reset signal, wherein each output of said first and second flip-flops has a pulse width corresponding to a phase difference between said first and second input signals.

Claim 3

The digital phase comparing circuit of claim 1, wherein each of said first and second rise detecting circuits comprises: a flip-flop constituted by two two-input NAND gates which are cross coupled, each of said rise detecting circuit flip-flops being set in response to a corresponding one of said first and second input signals and being reset in response to a corresponding one of said first and second detection signals, and a two-input NAND gate outputting said corresponding one of the first and second detection signals in response to said corresponding one of the first and second input signals and a positive logic output of said rise detecting circuit flip-flop.

Claim 4

The digital phase comparing circuit of claim 2, wherein said first and second flip-flops comprise two two-input NAND gates which are cross coupled, respectively, and said logical gate circuit comprises a two-input NAND gate outputting said reset signal in response to each of positive logic outputs of said flip-flops, each of said first and second flip-flops responding to said corresponding one of the first and second detection signals and said reset signal and outputting a pair of output signals.

Claim 5

The digital phase comparing circuit of claim 3, wherein said pair of output signals each have an opposite logical level and have a pulse width corresponding to a phase difference between said first and second input signals.

Claim 6

A digital phase comparing circuit, comprising: first and second input terminals receiving first and second input signals, respectively; a first rise detecting circuit for detecting a time of a rise of said first input signal and outputting a first detection signal, said first rise detecting circuit including a flip-flop having two two-input NAND gates which are cross coupled and being set in response to a corresponding input signal and being reset in response to the corresponding detection signal, and a two-input NAND gate outputting said corresponding detection signal in response to the corresponding input signal and a positive logic output of said flip-flop; a second rise detecting circuit for detecting a time of a rise of said second input signal and outputting a second detection signal input signal and outputting a second detection signal, said second rise detecting circuit including a flip-flop having two two-input NAND gates which are cross coupled and being set in response to a corresponding input signal and being reset in response to the corresponding detection signal, and a two-input NAND gate outputting said corresponding detection signal in response to the corresponding input signal and a positive logic output of said flip-flop; and a flip-flop circuit operatively connected to said first and second rise detecting circuits, being set in response to one input of said first and second detection signals and being reset in response to a subsequent input of said first and second detection signals, thereby simultaneously outputting a pair of output signals, each having an opposite logical level and having a pulse width corresponding to a phase difference between said first and second input signals.

Claim 7

A digital phase comparing circuit, comprising: first and second input terminals receiving first and second input signals, respectively; a first rise detecting circuit for detecting a time of a rise of said first input signal and outputting a first detection signal, said first rise detecting circuit including a flip-flop having two two-input NAND gates which are cross coupled and being set in response to a corresponding input signal and being reset in response to the corresponding detection signal, and a two-input NAND gate outputting said corresponding detection signal in response to the corresponding input signal and a positive logic output of said flip-flop; a second rise detecting circuit for detecting a time of a rise of said second input signal and outputting a second detection signal input signal and outputting a second detection signal, said second rise detecting circuit including a flip-flop having two two-input NAND gates which are cross coupled and being set in response to a corresponding input signal and being reset in response to the corresponding detection signal, and a two-input NAND gate outputting said corresponding detection signal in response to the corresponding input signal and a positive logic output of said flip-flop; and a flip-flop circuit operatively connected to said first and second rise detecting circuits, being set in response to one input of said first and second detection signals and being reset in response to a subsequent input of said first and second detection signals, thereby simultaneously outputting a pair of output signals, each having an opposite logical level and having a pulse width corresponding to a phase difference between said first and second input signals.