US4924428A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Real time digital signal processor idle indicator
Assignee: Nortel Networks Ltd
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Filing: 1987-12-08
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Granted: 1990-05-08
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Expires: 2007-12-08
Abstract
Abstract Instructions in the processor idle loop are used to measure the percentage of time the processor is at idle. The processor idle loop instructions control the processor to alternate a processor data output between output states. The processor data output thus alternates between states whenever the processor is idle, and remains in the same state when the processor is performing useful tasks. A frequency counter or other indicating device responsive to the rate of processor data output state change directly indicates the amount of time the processor is idle relative to the total amount of processing time. Since the change of state, not the state itself, of the data output is detected, it does not matter what state the data output is left in when the processor is interrupted from performing the idle loop instructions.
Inventors
- 👤 Matthew J. J. Vea
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 09:29
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/30; G06F11/34; G06F11/3409; G06F11/3419; G06F11/3423
Claims Analysis
Total Claims: 26
Claim 1
Independent Claim
187 words
An arrangement for measuring the percentage of time a digital signal processor is idle comprising: a digital signal processor having an output terminal and including means for executing program control instructions to perform predefined useful tasks; said digital signal processor further including idle loop executing means for executing idle loop program control instructions whenever said processor is not busy performing said useful tasks, said idle loop executing means for alternating the signal level at said digital signal processor output terminal between first and second binary levels whenever said processor is idling, for alternating the level at said processor output terminal at a rate over time which directly indicates the spare processing time of said digital signal processor, said digital signal processor maintaining said processor output terminal at a constant signal level whenever said processor performs said predefined tasks; and means external to said processor and connected to said processor output terminal for producing an indication of said spare processing time in response to the rate over time at which said processor alternates the signal level at said processor output terminal between said first and second binary levels.
Claim 2
Dependent Claim
187 words
An arrangement for measuring the percentage of time a digital signal processor is idle comprising: a digital signal processor having an output terminal and including means for executing program control instructions to perform predefined useful tasks; said digital signal processor further including idle loop executing means for executing idle loop program control instructions whenever said processor is not busy performing said useful tasks, said idle loop executing means for alternating the signal level at said digital signal processor output terminal between first and second binary levels whenever said processor is idling, for alternating the level at said processor output terminal at a rate over time which directly indicates the spare processing time of said digital signal processor, said digital signal processor maintaining said processor output terminal at a constant signal level whenever said processor performs said predefined tasks; and means external to said processor and connected to said processor output terminal for producing an indication of said spare processing time in response to the rate over time at which said processor alternates the signal level at said processor output terminal between said first and second binary levels.
Claim 3
Dependent Claim
32 words
An arrangement as in claim 1 wherein said indication producing means includes frequency counting means for counting the number of times said processor output terminal level alternates over a predetermined gate time.
Claim 4
Dependent Claim
72 words
An arrangement as in claim 1 wherein: said arrangement further includes clock generating means connected to said digital signal processor for controlling the rate at which said executing means executes said program control instructions and the rate at which said idle loop executing means continually alternates the level at said processor output terminal when said processor is idle; and said frequency counting gate time has a predetermined relationship to said controlled rate.
Claim 5
Dependent Claim
150 words
A real time digital signal processing system comprising: memory means for storing an idle loop program control routine and a further program control routine defining input signal processing tasks; a processor means connected to said memory means, also connected to receive externally generated input signals, and having a data output connection, for processing said input signals substantially in real time in accordance with said further program control routine and for performing said idle loop program control routine whenever not occupied processing said input signals, said idle loop program control routine causing said data output connection to continually alternate between first and second states during the time said processor is performing said idle loop program routine; and indicating means connected to said output connection for producing an indication of the percentage of time said processor performs said idle program control routine in response to changes in said data output connection state.
Claim 6
Dependent Claim
150 words
A real time digital signal processing system comprising: memory means for storing an idle loop program control routine and a further program control routine defining input signal processing tasks; a processor means connected to said memory means, also connected to receive externally generated input signals, and having a data output connection, for processing said input signals substantially in real time in accordance with said further program control routine and for performing said idle loop program control routine whenever not occupied processing said input signals, said idle loop program control routine causing said data output connection to continually alternate between first and second states during the time said processor is performing said idle loop program routine; and indicating means connected to said output connection for producing an indication of the percentage of time said processor performs said idle program control routine in response to changes in said data output connection state.
Claim 7
Dependent Claim
24 words
A system as in claim 4 wherein said indicating means includes means for counting the number of data output connection state changes over time.
Claim 8
Dependent Claim
25 words
A system as in claim 4 wherein said indicating means indicates the time said processor means performs said idle loop program control routine over time.
Claim 9
Dependent Claim
79 words
A system as in claim 4 wherein said idle loop program control routine defines: a first idle task which causes said processor data output connection to rise to a logic level 1; a second idle task which causes said processor data output connection to fall to a logic level 0; and a third idle task which causes said first and second idle tasks to be periodically executed whenever said processor is idle and is not performing said further tasks.
Claim 10
Dependent Claim
25 words
A system as in claim 4 wherein said indicating means includes optical indicating means for indicating the frequency of said data output connection state changes.
Claim 11
Dependent Claim
75 words
A system as in claim 4 wherein: said system further includes means for generating an alternating clock synchronization signal having a preset frequency, said processor means being connected to receive said clock signal and performing said idle and further tasks at a rate responsive to said clock signal; and said indicating means includes means for determining the ratio between the frequency at which said processor data output connection changes state and the clock signal frequency.
Claim 12
Dependent Claim
25 words
A system as in claim 4 wherein processing of said idle loop program control routine does not increase the effective loading of said processor means.
Claim 13
Dependent Claim
60 words
A system as in claim 4 wherein: said processor means is interrupt driven, receipt of an input signal causing said processor means to execute said further program control routine, said processor means performing said idle loop program control routine whenever no interrupt is occurring and performance of said further program control routine in response to previously received interrupts is completed.
Claim 14
Dependent Claim
65 words
A system as in claim 4 wherein said indicating means includes: an exclusive OR gate having first and second input terminals and an output terminal, said first input terminal being coupled to said processor means data output; a resistor connected between said exclusive OR gate first and second input terminals; and a capacitor connected between said exclusive OR gate second input terminal and ground potential.
Claim 15
Dependent Claim
24 words
A system as in claim 12 wherein said indicating means further includes a light emitting diode connected to said exclusive OR gate output terminal.
Claim 16
Dependent Claim
21 words
A system as in claim 4 wherein said processor data output changes state asymmetrically when said processing means is 100% idling.
Claim 17
Dependent Claim
47 words
A system as in claim 4 wherein said idle tasks cause said data output to change state at a preset instantaneous rate, the average rate at which said data output changes state being directly proportional to the duration said processor means performs said idle routine over time.
Claim 18
Dependent Claim
123 words
A digital signal processing system comprising: a digital signal processing means of the type which alternately operates in a busy state and in an idle state, said processing means for processing input signals applied thereto when operating in said busy state, said processing means for performing an idle loop routine when operating in said idle state, said processing means including means for producing a continually alternating binary valued output signal when said processing means is operating in said idle state; and indicating means connected to receive said output signal for indicating the percentage of time said processing means is operating in said idle state in response to the rate over time said output signal is alternated in response to said idle loop routine.
Claim 19
Dependent Claim
123 words
A digital signal processing system comprising: a digital signal processing means of the type which alternately operates in a busy state and in an idle state, said processing means for processing input signals applied thereto when operating in said busy state, said processing means for performing an idle loop routine when operating in said idle state, said processing means including means for producing a continually alternating binary valued output signal when said processing means is operating in said idle state; and indicating means connected to receive said output signal for indicating the percentage of time said processing means is operating in said idle state in response to the rate over time said output signal is alternated in response to said idle loop routine.
Claim 20
Dependent Claim
102 words
A digital signal processing method comprising: (1) operating a digital signal processor alternately in a busy state and in an idle state; (2) processing input signals with said processor whenever said processor operates in said busy state; (3) producing a continually alternating binary valued output signal directly at an output terminal of said processor under control of a processor idle loop routine only when said processor operates in said idle state; and (4) indicating the percentage of time said processor operates in said idle state in response to the average rate over time said output signal is alternated by said step (3).
Claim 21
Dependent Claim
102 words
A digital signal processing method comprising: (1) operating a digital signal processor alternately in a busy state and in an idle state; (2) processing input signals with said processor whenever said processor operates in said busy state; (3) producing a continually alternating binary valued output signal directly at an output terminal of said processor under control of a processor idle loop routine only when said processor operates in said idle state; and (4) indicating the percentage of time said processor operates in said idle state in response to the average rate over time said output signal is alternated by said step (3).
Claim 22
Dependent Claim
27 words
A method as in claim 17 wherein said indicating step (4) includes counting the number of transitions of said output signal occurring during a preset gate time.
Claim 23
Dependent Claim
21 words
A method as in claim 17 wherein said indicating step (4) includes producing light every time said output signal changes value.
Claim 24
Dependent Claim
35 words
A method as in claim 17 further including: performing said processing step (2) in response to an interrupt request; and performing said producing step (3) after said processing step (2) finishes processing said input signals.
Claim 25
Dependent Claim
46 words
A method as in claim 17 wherein said producing step (3) includes: (a) applying a logic level 1 to a data output of said processor; (b) applying a logic level 0 to said processor data output; and (c) periodically repeating said applying steps (a) and (b).
Claim 26
Dependent Claim
21 words
A method as in claim 17 wherein said producing step (3) is performed under control of idle loop program control instructions.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-05-07 | 1993-11-06 | 1994-05-08 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-05-07 | 1997-11-06 | 1998-05-08 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-05-07 | 2001-11-06 | 2002-05-08 | $7700.00 | Window Closed / Lapsed |