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US4924399A
Expired / Lapsed
US
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Vehicle control system with HSO-triggered output
Assignee: Robert Bosch GmbH
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Filing: 1988-04-21
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Granted: 1990-05-08
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Expires: 2008-04-21
Abstract
Abstract The resistance to supply voltage, e.g. battery, fluctuation of an input/output circuit for a control system, e.g. vehicular ignition/fuel injection system, is improved by placing a comparator K in each analog input line, and using a voltage divider UD to compensate the reference voltage U R applied to one of the comparator inputs. Processing speed is increased by using digital comparators 22-26, which test not only for threshold value equal to counter state, but also for threshold value greater than counter state, in the duty-cycle modification circuit. Chip count is reduced and integration is increased by using a single voltage divider to supply all the input comparators and by using a High-Speed Output (HSO) port on the central processing unit (CPU) to perform multiple output tasks.
Inventors
- 👤 Gunther Kaiser
- 👤 Winfried Klotzner
- 👤 Immanuel Krauter
- 👤 Edmund Jeenicke
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 18:22
CPC Classifications
G; G06; G06F; G06F3/00; G06F3/05; F; F02; F02D; F02D41/00; F02D41/24; F02D41/26; F02D41/28; G05; G05B; G05B1/00; G05B1/01; G05B1/03
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
186 words
An output circuit for a vehicular control system performing regularly recurring ignition and fuel injection tasks and having a microprocessor central processing unit (CPU) with a plurality of control outputs and a High-Speed Output (HSO) port; an output interface (t, AI); and an Internal Data bus (ID) interconnecting said microprocessor and said output interface, comprising, an output register (10) having a plurality of data inputs, a latch-enable input connected to said HSO port of said CPU, and outputs connected to said output interface (5, AI); and a preparatory register (9) having a plurality of inputs, and an output connected directly to said output register (10), connected in said Internal Data bus (ID) between said CPU and said output register (10); said preparatory register (9) accepting and storing data from said CPU, said stored data being transferred directly from said register (9) to said output register (10) in response to a transfer signal from said CPU, said transfer signal being generated periodically in connection with said regularly recurring ignition and fuel injection tasks, thereby making all said stored data available simultaneously to said output interface (5, AI).
Claim 2
Dependent Claim
186 words
An output circuit for a vehicular control system performing regularly recurring ignition and fuel injection tasks and having a microprocessor central processing unit (CPU) with a plurality of control outputs and a High-Speed Output (HSO) port; an output interface (t, AI); and an Internal Data bus (ID) interconnecting said microprocessor and said output interface, comprising, an output register (10) having a plurality of data inputs, a latch-enable input connected to said HSO port of said CPU, and outputs connected to said output interface (5, AI); and a preparatory register (9) having a plurality of inputs, and an output connected directly to said output register (10), connected in said Internal Data bus (ID) between said CPU and said output register (10); said preparatory register (9) accepting and storing data from said CPU, said stored data being transferred directly from said register (9) to said output register (10) in response to a transfer signal from said CPU, said transfer signal being generated periodically in connection with said regularly recurring ignition and fuel injection tasks, thereby making all said stored data available simultaneously to said output interface (5, AI).
Claim 3
Dependent Claim
20 words
Output circuit according to claim 1, wherein said transfer signal is a trigger signal generated in synchrony with crankshaft rotation.
Claim 4
Dependent Claim
148 words
An output circuit for a vehicular control system performing regularly recurring ignition and fuel injection tasks and having a microprocessor central processing unit (CPU) with a plurality of control outputs; an output interface (5, AI); and a data bus interconnecting said CPU and said output interface; and an output register (10) interposed, in said data bus, between said CPU and said output interface, comprising, preparatory registers (17-21) interposed between said CPU and said output register (10) and accepting and storing data from said CPU; a plurality of counters (C1-C3); and a plurality of comparators (22-26), each having one input connected to an output of a respective one of said preparatory registers and another input connected to an output of one of said counters, said output register (10) being switched in dependence upon a comparison between values stored in said counters and values stored in said preparatory registers (17-21).
Claim 5
Dependent Claim
148 words
An output circuit for a vehicular control system performing regularly recurring ignition and fuel injection tasks and having a microprocessor central processing unit (CPU) with a plurality of control outputs; an output interface (5, AI); and a data bus interconnecting said CPU and said output interface; and an output register (10) interposed, in said data bus, between said CPU and said output interface, comprising, preparatory registers (17-21) interposed between said CPU and said output register (10) and accepting and storing data from said CPU; a plurality of counters (C1-C3); and a plurality of comparators (22-26), each having one input connected to an output of a respective one of said preparatory registers and another input connected to an output of one of said counters, said output register (10) being switched in dependence upon a comparison between values stored in said counters and values stored in said preparatory registers (17-21).
Claim 6
Dependent Claim
32 words
Output circuit according to claim 3, wherein at least one of said counters (C2, C3) is connected to multiple ones of said comparators (23-26), and said counters have different respective clock rates.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-05-07 | 1993-11-06 | 1994-05-08 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-05-07 | 1997-11-06 | 1998-05-08 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-05-07 | 2001-11-06 | 2002-05-08 | $7700.00 | Window Closed / Lapsed |