Two-port switched capacitor filter netowrk with linearized phase/frequency response

Claim 2

A two-port switched capacitor filter network comprising: two input terminals; two output terminals; a first integrator circuit having three inputs provided with capacitors which are switched under control of first and second clock states which are distinct from each other, a first input of the first integrator circuit being connected to a first of the input terminals, and an output of the first integrator circuit being connected to a first of the output terminals; a second integrator circuit having two inputs provided with capacitors which are switched under control of the first and second clock states, with a first input of the second integrator circuit being connected to the output of the first integrator circuit and with an output of the second integrator circuit constituting a second input of the first integrator circuit; a third integrator circuit having three inputs provided with capacitors which are switched under control of the first and second clock states, the first input of the third integrator circuit being connected to the output of the second integrator circuit, the second input of the third integrator circuit being connected to a second of the input terminals and an output of the third integrator circuit being connected to a second of the output terminals and also to a second input of the second integrator circuit; a fourth integrator circuit having three inputs provided with capacitors which are switched under control of the first and second clock states, the first input of the fourth integrator circuit being connected to the output of the first integrator circuit and the second input of the fourth integrator circuit being connected to the output of the third integrator circuit, and an output of the fourth integrator circuit being connected to a third input of each of the first and third integrator circuits; and a fifth integrator circuit having a single input provided with a capacitor which is switched under control of first and second clock states, also connected to the output of the fourth integrator circuit and having an output connected to a third input of the fourth integrator circuit; said five integrator circuits being interconnected to constitute a sampling filter having a linear phase/frequency response.

Claim 3

A two-port network according to claim 1, wherein at least some of the integrator circuits comprise an operational amplifier having a non-inverting input connected to ground and an inverting input connected to the inputs of the integrator circuits via switched capacitors.

Claim 4

A two-port network according to claim 2, wherein each of the inputs of an integrator circuit comprise: a capacitor; an input switch suitable for establishing an electrical connection between one plate of the capacitor and either the input or ground; and a link switch member suitable for establishing an electrical connection between the other plate of the capacitor and either the inverting input or ground.

Claim 5

A two-port network according to claim 3, wherein the link switch member comprises a switch suitable for establishing electrical connection between a node and either the inverting input or ground, with the other plates of all the input capacitors of the integrator circuit being interconnected at the node.

Claim 6

A two-port network according to claim 3, wherein the link switch member comprises a plurality of switches each suitable for establishing an electrical connection between the other plate of the corresponding input capacitor of the integrator circuit and either a respective electric contact point or ground, with the electric contact points being interconnected and being connected to the inverting input of the integrator circuit.

Claim 7

A two-port network according to claim 2, wherein each inverting input of the integrator circuits is connected by a capacitor to the output of the operational amplifier of each integrator circuit.

Claim 8

A two-port network according to claim 1, wherein the output of the first integrator circuit is connected by a capacitor to the inverting input of the amplifier of the third integrator circuit, and wherein the output from the third integrator circuit is connected via another capacitor to the inverting input of the amplifier of the first integrator circuit, thereby obtaining a switched capacitor sampling filter of the elliptical type.

Claim 9

A two-port switched capacitor filter network comprising: two input terminals; two output terminals; a first integrator circuit having three inputs provide with capacitors which are switched under control of first and second clock states which are distinct from each other, the first input of the first integrator circuit being connected to a first of the input terminals and an output of the first integrator circuit connected to the first of the output terminals; a second integrator circuit having two inputs provided with capacitors which are switched under control of the first and second clock states, with a first input of the second integrator circuit being connected to the output of the first integrator circuit and with an output of the second integrator circuit constituting a second input of the first integrator circuit; a third integrator circuit having three inputs provided with capacitors which are switched under control of the first and second clock states, a first input of the third integrator circuit being connected to the output of the second integrator circuit, a second input of the third integrator circuit being connected to a second of the input terminals; and an output of the third integrator circuit being connected to a second of the output terminals and also to a second input of the second integrator circuit; a fourth integrator circuit having three inputs provided with capacitors which are switched under control of the first and second clock states, the first input of the fourth integrator circuit being connected to the output of the first integrator circuit and a second input of the fourth integrator circuit being connected to the output of the third integrator circuit, and an output of the fourth integrator circuit being connected to a third input of each of the first and third integrator circuits; a fifth integrator circuit having a single input provided with a capacitor which is switched under control of first and second clock states, also connected to the output of the fourth integrator circuit and having an output connected to a third input of the fourth integrator circuit; said five integrator circuits being interconnected to constitute a sampling filter having a linear phase/frequency response; and a plurality of supplementary integrator circuits, each having two inputs fitted with capacitors switched under the control of the clock states, the plurality of supplementary integrator circuits being interconnected with each other and in series with the first, second, third, fourth and fifth integrator circuits in order to constitute a multiple-order sampling filter having a linear phase/frequency response.

Claim 10

A two-port switched capacitor filter network comprising: two input terminals; two output terminals; a first integrator circuit having three inputs provide with capacitors which are switched under control of first and second clock states which are distinct from each other, the first input of the first integrator circuit being connected to a first of the input terminals and an output of the first integrator circuit connected to the first of the output terminals; a second integrator circuit having two inputs provided with capacitors which are switched under control of the first and second clock states, with a first input of the second integrator circuit being connected to the output of the first integrator circuit and with an output of the second integrator circuit constituting a second input of the first integrator circuit; a third integrator circuit having three inputs provided with capacitors which are switched under control of the first and second clock states, a first input of the third integrator circuit being connected to the output of the second integrator circuit, a second input of the third integrator circuit being connected to a second of the input terminals; and an output of the third integrator circuit being connected to a second of the output terminals and also to a second input of the second integrator circuit; a fourth integrator circuit having three inputs provided with capacitors which are switched under control of the first and second clock states, the first input of the fourth integrator circuit being connected to the output of the first integrator circuit and a second input of the fourth integrator circuit being connected to the output of the third integrator circuit, and an output of the fourth integrator circuit being connected to a third input of each of the first and third integrator circuits; a fifth integrator circuit having a single input provided with a capacitor which is switched under control of first and second clock states, also connected to the output of the fourth integrator circuit and having an output connected to a third input of the fourth integrator circuit; said five integrator circuits being interconnected to constitute a sampling filter having a linear phase/frequency response; and a plurality of supplementary integrator circuits, each having two inputs fitted with capacitors switched under the control of the clock states, the plurality of supplementary integrator circuits being interconnected with each other and in series with the first, second, third, fourth and fifth integrator circuits in order to constitute a multiple-order sampling filter having a linear phase/frequency response.