Electrically programmable erasable inverter device with deprogramming limitation

Claim 2

Inverter circuit, in which the inverter is programmable, characterized by: (a) a first n-channel transistor having a floating gate extending over a substrate and a control gate extending over the floating gate, the floating gate being electrically isolated from the substrate and from the control gate, and having a gate oxide window adjacent to the drain, the control gate receiving an input signal; (b) a p-channel transistor; (c) the p-channel transistor having a floating gate and a control gate, the floating gate extending between the control gate and source and drain regions of the p-channel transistor, said control gate of the p-channel transistor being connected to the control gate of the first n-channel transistor so as to receive the input signal; (d) the floating gates of the n- and p-channel transistors being in electrical communication with each other; (e) a second n-channel transistor connected in series with the floating gate n-channel transistor, the second n-channel transistor having a transition voltage not controlled by the floating gates, the second n-channel transistor having a control gate connected to the control gate of the first n-channel transistor and the p-channel transistor; (f) the second n-channel transistor being fabricated as a section of the floating gate n-channel transistor, with the floating gate not extending across an area defined by a gate portion of the second n-channel transistor; and (g) an output terminal connected in common to the first and second n-channel transistors and to the p-channel transistor.

Claim 3

Circuit as described in claim 1, further characterized by: a second p-channel transistor connected in parallel with the floating gate p-channel transistor, the second p-channel transistor having a transition voltage not controlled by the floating gates.

Claim 4

Circuit as described in claim 2, further characterized by: the transistors being fabricated on a single integrated circuit chip.

Claim 5

Circuit as described in claim 2, further characterized by: (a) the transistors being fabricated on a single integrated circuit chip, wherein the floating gates are formed as a single layer of polysilicon deposited over a doped silicon substrate; (b) a first oxide layer is interposed between the floating gates and the substrate; (c) the control gates are formed as a second layer of polysilicon; (d) a second oxide layer interposed between the floating gates and the control gates.

Claim 6

Circuit as described in claim 4, further characterized by: (a) a transistor connected in series between the floating gates; and (b) the floating gates being in said electrical communication only when the transistor is conducting.

Claim 7

Circuit as described in claim 1, further characterized by: (a) the transistors being fabricated on a single integrated circuit chip, wherein the floating gates are formed as a single layer of polysilicon deposited over a doped silicon substrate; (b) a first oxide layer is interposed between the floating gates and the substrate; (c) the control gates are formed as a second layer of polysilicon; (d) a second oxide layer interposed between the floating gates and the control gates.

Claim 8

Circuit as described in claim 1, further characterized by: a second p-channel transistor connected in parallel with the floating gate p-channel transistor, the second p-channel transistor having a transition voltage not controlled by the floating gates.

Claim 9

Circuit as described in claim 1, further characterized by: (a) a transistor connected in series between the floating gates; and (b) the floating gates being in said electrical communication only when the transistor is conducting.

Claim 10

Circuit including p-channel and n-channel transistors, in which at least one p-channel transistors are programmable with respect to its transition voltage, characterized by: (a) a first n-channel transistor having a floating gate extending over a substrate and a control gate extending over the floating gate, the floating gate being electrically isolated from the substrate and from the control gate, and having a gate oxide window adjacent to the drain, the control gate receiving an input signal; (b) the p-channel transistor having a floating gate and a control gate, the floating gate extending between the control gate and source and drain regions of the p-channel transistor, said control gate of the p-channel transistor being connected to the control gate of the first n-channel transistor so as to receive the input signal; (c) the floating gates of the n- and p-channel transistors being in electrical communication with each other; (d) a second n-channel transistor connected in series with the floating gate n-channel transistor, the second n-channel transistor having a transition voltage not controlled by the floating gates, the second n-channel transistor having a control gate connected to the control gate of the first n-channel transistor and the p-channel transistor; (e) the second n-channel transistor being fabricated as a section of the floating gate n-channel transistor, with the floating gate not extending across an area defined by a gate portion of the second n-channel transistor; and (f) an output terminal connected in common to the first and second n-channel transistors and to the p-channel transistor.

Claim 11

Circuit including p-channel and n-channel transistors, in which at least one p-channel transistors are programmable with respect to its transition voltage, characterized by: (a) a first n-channel transistor having a floating gate extending over a substrate and a control gate extending over the floating gate, the floating gate being electrically isolated from the substrate and from the control gate, and having a gate oxide window adjacent to the drain, the control gate receiving an input signal; (b) the p-channel transistor having a floating gate and a control gate, the floating gate extending between the control gate and source and drain regions of the p-channel transistor, said control gate of the p-channel transistor being connected to the control gate of the first n-channel transistor so as to receive the input signal; (c) the floating gates of the n- and p-channel transistors being in electrical communication with each other; (d) a second n-channel transistor connected in series with the floating gate n-channel transistor, the second n-channel transistor having a transition voltage not controlled by the floating gates, the second n-channel transistor having a control gate connected to the control gate of the first n-channel transistor and the p-channel transistor; (e) the second n-channel transistor being fabricated as a section of the floating gate n-channel transistor, with the floating gate not extending across an area defined by a gate portion of the second n-channel transistor; and (f) an output terminal connected in common to the first and second n-channel transistors and to the p-channel transistor.

Claim 12

Circuit as described in claim 9, further characterized by: a second p-channel transistor connected in parallel with the floating gate p-channel transistor, the second p-channel transistor having a transition voltage not controlled by the floating gates.

Claim 13

Circuit as described in claim 10, further characterized by: the transistors being fabricated on a single integrated circuit chip.

Claim 14

Circuit as described in claim 10, further characterized by: (a) the transistors being fabricated on a single integrated circuit chip, wherein the floating gates are formed as a single layer of polysilicon deposited over a doped silicon substrate; (b) a first oxide layer is interposed between the floating gates and the substrate; (c) the control gates are formed as a second layer of polysilicon; (d) a second oxide layer is interposed between the floating gates and the control gates.

Claim 15

Circuit as described in claim 9, further characterized by: (a) the transistors being fabricated on a single integrated circuit chip, wherein the floating gates are formed as a single layer of polysilicon deposited over a doped silicon substrate; (b) a first oxide layer is interposed between the floating gates and the substrate; (c) the control gates are formed as a second layer of polysilicon; (d) the second oxide layer is interposed between the floating gates and the control gates.

Claim 16

Circuit as described in claim 9, further characterized by: a second p-channel transistor connected in parallel with the floating gate p-channel transistor, the second p-channel transistor having a transition voltage not contolled by the floating gates.

Claim 17

Circuit as described in claim 14, further characterized by: (a) a transistor connected in series between the floating gates; and (b) the floating gates being in said electrical communication only when the transistor is conducting.

Claim 18

Circuit as described in claim 15, further characterized by: the transistor connected in series between the floating gates being gated by potentials required for at least one Fowler-Nordheim operation applied to the n-channel transistor.

Claim 19

Inverter circuit, in which the inverter is programable, characterized by: (a) an n-channel transistor having a floating gate extending over a substrate and a control gate extending over the floating gate, the floating gate being electrically isolated from the substrate and from the control gate, and having a gate oxide window adjacent to the drain, the control gate receiving an input signal; (b) a p-channel transistor; (c) the p-channel transistor having a floating gate and a control gate, the floating gate extending between the control gate and source and drain regions of the p-channel transistor, said control gate of the p-channel transistor being connected to the control gate of the n-channel transistor so as to receive the input signal; (d) the floating gates of the n- and p-channel transistors being in electrical communication with each other; (e) an output terminal connected in common to the n-channel transistor and to the p-channel transistor; (f) a transistor connected in series between the floating gates; and (g) the floating gates being in said electrical communication only when the transistor is conducting.

Claim 20

Inverter circuit, in which the inverter is programable, characterized by: (a) an n-channel transistor having a floating gate extending over a substrate and a control gate extending over the floating gate, the floating gate being electrically isolated from the substrate and from the control gate, and having a gate oxide window adjacent to the drain, the control gate receiving an input signal; (b) a p-channel transistor; (c) the p-channel transistor having a floating gate and a control gate, the floating gate extending between the control gate and source and drain regions of the p-channel transistor, said control gate of the p-channel transistor being connected to the control gate of the n-channel transistor so as to receive the input signal; (d) the floating gates of the n- and p-channel transistors being in electrical communication with each other; (e) an output terminal connected in common to the n-channel transistor and to the p-channel transistor; (f) a transistor connected in series between the floating gates; and (g) the floating gates being in said electrical communication only when the transistor is conducting.

Claim 21

Circuit including p-channel and n-channel transistors, in which at least one p-channel transistors are programable with respect to its transition voltage, characterized by: (a) a first n-channel transistor having a floating gate extending over a substrate and a control gate extending over the floating gate, the floating gate being electrically isolated from the substrate and from the control gate, and having a gate oxide window adjacent to the drain, the control gate receiving an input signal; (b) the p-channel transistor having a floating gate and a control gate, the floating gate extending between the control gate and source and drain regions of the p-channel transistor, said control gate of the p-channel transistor being connected to the control gate of the first n-channel transistor so as to receive the input signal; (c) the floating gates of the n- and p-channel transistors being in electrical communication with each other; (d) a second n-channel transistor connected in series with the floating gate n-channel transistor, the second n-channel transistor having a transition voltage not controlled by the floating gates, the second in-channel transistor having a control gate connected to the control gate of the first n-channel transistor and the p-channel transistor; (e) an output terminal connected in common to the first and second n-channel transistors and to the p-channel transistor; (f) a transistor connected in series between the floating gates; and (g) the floating gates being in said electrical communication only when the transistor is conducting.

Claim 22

Circuit including p-channel and n-channel transistors, in which at least one p-channel transistors are programable with respect to its transition voltage, characterized by: (a) a first n-channel transistor having a floating gate extending over a substrate and a control gate extending over the floating gate, the floating gate being electrically isolated from the substrate and from the control gate, and having a gate oxide window adjacent to the drain, the control gate receiving an input signal; (b) the p-channel transistor having a floating gate and a control gate, the floating gate extending between the control gate and source and drain regions of the p-channel transistor, said control gate of the p-channel transistor being connected to the control gate of the first n-channel transistor so as to receive the input signal; (c) the floating gates of the n- and p-channel transistors being in electrical communication with each other; (d) a second n-channel transistor connected in series with the floating gate n-channel transistor, the second n-channel transistor having a transition voltage not controlled by the floating gates, the second in-channel transistor having a control gate connected to the control gate of the first n-channel transistor and the p-channel transistor; (e) an output terminal connected in common to the first and second n-channel transistors and to the p-channel transistor; (f) a transistor connected in series between the floating gates; and (g) the floating gates being in said electrical communication only when the transistor is conducting.

Claim 23

Circuit as described in claim 18, further characterized by: the transistor connected in series between the floating gates being gated by potentials required for at least one Fowler-Nordheim operation applied to the n-channel transistor.