Transistor base current compensation circuitry

Claim 2

Circuitry comprising: an operational amplifier having first and second inputs and an output; a current mirror having an input coupled to the output of the operational amplifier, having a first output coupled to the second input of the operational amplifier and to a first load element and having a second output coupled to the first input of the operational amplifier; and a circuitry input/output terminal being coupled to the first input of the operational amplifier.

Claim 3

The circuitry of claim 1 wherein the first input of the operational amplifier is connectible to a second load element which is essentially an electrical equivalent of the first load element and which is a part of or is driven by a separate circuit.

Claim 4

The circuitry of claim 2 wherein each one of said first and second load elements comprises a separate bipolar transistor and a resistor.

Claim 5

The circuitry of claim 3 wherein the operational amplifier comprises field effect transistors.

Claim 6

The circuitry of claim 4 wherein the operational amplifier further comprises a bipolar transistor.

Claim 7

The circuitry of claim 5 wherein the field effect transistors are metal-oxide silicon transistors and the load elements each comprise at least one n-p-n bipolar transistor.

Claim 8

The circuitry of claim 5 wherein all the transistors are formed in a single integrated circuit chip with the n-p-n transistors all having common collectors.

Claim 9

The circuitry of claim 7, wherein the separate circuit is formed on the same integrated circuit chip as the circuitry and comprises n-p-n transistors having collectors which are common with the collectors of the n-p-n transistors of the circuitry.

Claim 10

Circuitry, which is connectible to and adapted to supply current to a first load element which is part of or driven by a separate circuit, comprising: an operational amplifier having first and second inputs and an output; a current mirror having an input coupled to the output of the operational amplifier, having a first output coupled to the second input of the operational amplifier and to a second load element and having a second output coupled to the first input of the operational amplifier and to the first load element; and the first and second load elements being electrically equivalent.

Claim 11

Circuitry, which is connectible to and adapted to supply current to a first load element which is part of or driven by a separate circuit, comprising: an operational amplifier having first and second inputs and an output; a current mirror having an input coupled to the output of the operational amplifier, having a first output coupled to the second input of the operational amplifier and to a second load element and having a second output coupled to the first input of the operational amplifier and to the first load element; and the first and second load elements being electrically equivalent.

Claim 12

In combination: a reference voltage generator comprising first and second n-p-n transistors and first, second, third, fourth and fifth resistors and a first operational amplifier having first and second inputs and an output; each of the first and second n-p-n transistors having a base and an emitter; the bases of the first and second transistors being coupled to first terminals of the first and second resistors; the emitter of the first transistor being coupled to a first terminal of the third resistor and to the first input of the operational amplifier; the emitter of the second transistor being coupled to a first terminal of the fourth resistor; a second terminal of the fourth resistor being coupled to a first terminal of the fifth resistor and to the second input of the operational amplifier; the output of the operational amplifier being coupled to a second terminal of the first resistor; current compensation circuitry coupled to the bases of the first and second transistors comprising a second operational amplifier having first and second inputs and an output, a current mirror having an input and first and second outputs, a third n-p-n transistor and a sixth resistor; the third n-p-n transistor having a base and an emitter; the output of the second operational amplifier being coupled to the input of the current mirror; the first output of the current mirror being coupled to the second input of the second operational amplifier and to the base of the third n-p-n transistor; the second output of the current mirror being coupled to the bases of the first and second transistors and to the first input of the operational amplifier; the emitter of the third transistor being coupled to a first terminal of the sixth resistor; and the combination of the third n-p-n transistor and the sixth resistor being designed to be essentially the electrical equivalent of the combination of the first transistor and third resistor and the second transistor and the fourth and fifth resistors.

Claim 13

In combination: a reference voltage generator comprising first and second n-p-n transistors and first, second, third, fourth and fifth resistors and a first operational amplifier having first and second inputs and an output; each of the first and second n-p-n transistors having a base and an emitter; the bases of the first and second transistors being coupled to first terminals of the first and second resistors; the emitter of the first transistor being coupled to a first terminal of the third resistor and to the first input of the operational amplifier; the emitter of the second transistor being coupled to a first terminal of the fourth resistor; a second terminal of the fourth resistor being coupled to a first terminal of the fifth resistor and to the second input of the operational amplifier; the output of the operational amplifier being coupled to a second terminal of the first resistor; current compensation circuitry coupled to the bases of the first and second transistors comprising a second operational amplifier having first and second inputs and an output, a current mirror having an input and first and second outputs, a third n-p-n transistor and a sixth resistor; the third n-p-n transistor having a base and an emitter; the output of the second operational amplifier being coupled to the input of the current mirror; the first output of the current mirror being coupled to the second input of the second operational amplifier and to the base of the third n-p-n transistor; the second output of the current mirror being coupled to the bases of the first and second transistors and to the first input of the operational amplifier; the emitter of the third transistor being coupled to a first terminal of the sixth resistor; and the combination of the third n-p-n transistor and the sixth resistor being designed to be essentially the electrical equivalent of the combination of the first transistor and third resistor and the second transistor and the fourth and fifth resistors.

Claim 14

The combination of claim 10 wherein the first, second and third n-p-n transistors all have collectors which are coupled together, and second terminals of the third, fifth and sixth resistors are coupled together.

Claim 15

The combination of claim 11 wherein the second resistor has a second terminal which is coupled to the second terminal of the third resistor.

Claim 16

The combination of claim 12 wherein the second operational amplifier comprises: first, second, third and fourth field effect transistors (FETs), a fourth n-p-n transistor and a seventh resistor; each of the FETs having a gate, a drain and a source; the fourth n-p-n transistor having a base, an emitter and a collector; the sources of the first and second FETs being coupled to the collector of the fourth n-p-n transistor; the sources of the third and fourth FETs being coupled to a first terminal of the seventh resistor; a second terminal of the seventh resistor being coupled to a second terminal of the sixth resistor; the gates of the first and second FETs being coupled to the drains of the first and third FETs; the drains of the second and fourth FETs being coupled to the base of the fourth n-p-n transistor; the emitter of the fourth n-p-n transistor being coupled to the input of the current mirror; and the gate of the fourth FET being coupled to the first output of the current mirror and to the base of the third n-p-n transistor the gate of the third FET being coupled to the second output of the current mirror.

Claim 17

The combination of claim 13 wherein the current mirror comprises: fifth and sixth field effect transistors (FETs) each having a gate, a source and a drain; the sources of the fifth and sixth FETs serving as the input of the current mirror and being coupled to the emitter of the n-p-n fourth transistor; the gates of the fifth and sixth FETs and the drain of the fifth FET serving as the first output of the current mirror and being coupled to the gate of the fourth FET and to the base of the third n-p-n transistor; and the drain of the sixth FET serving as the second output of the current mirror and being coupled to the gate of the third FET.

Claim 18

The combination of claim 14 wherein the first, second, third, fourth, fifth and sixth FETs are n-channel metal-oxide-silicon transistors.

Claim 19

Circuitry comprising: a first load element; first circuit means having first and second inputs and an output with the output being coupled to the second input thereof for generating at the second input thereof a potential level which is essentially the same as one applied to the first input thereof; a circuitry input/output terminal being coupled to the first input of the first circuit means; second circuit means coupled to the first and second inputs of the first circuit means for sensing current drawn by the first load element and for generating an essentially identical current flow into a node coupled to the first input of the first circuit means; and the output of the first circuit means being coupled to the second input thereof through the second circuit means.

Claim 20

Circuitry comprising: a first load element; first circuit means having first and second inputs and an output with the output being coupled to the second input thereof for generating at the second input thereof a potential level which is essentially the same as one applied to the first input thereof; a circuitry input/output terminal being coupled to the first input of the first circuit means; second circuit means coupled to the first and second inputs of the first circuit means for sensing current drawn by the first load element and for generating an essentially identical current flow into a node coupled to the first input of the first circuit means; and the output of the first circuit means being coupled to the second input thereof through the second circuit means.

Claim 21

Circuitry, which is connectible to and adapted to supply drive current to a first load element which is part of or is driven by a separate circuit, comprising: a second load element which is the electrical equivalent of the first load element; first circuit means having first and second inputs and an output with the output being coupled to the second input thereof for generating at the second input thereof a potential level (voltage) which is essentially the same as one applied to the first input thereof; a circuitry input/output terminal being coupled to the first input of the first circuit means; second circuit means coupled to the first and second inputs of the first circuit means of sensing current drawn by the second load element and for generating an essentially identical current flow into a node coupled to the first input of the first circuit means and to the first load element; and the output of the first circuit means being coupled to the second input thereof through the second circuit means.

Claim 22

Circuitry, which is connectible to and adapted to supply drive current to a first load element which is part of or is driven by a separate circuit, comprising: a second load element which is the electrical equivalent of the first load element; first circuit means having first and second inputs and an output with the output being coupled to the second input thereof for generating at the second input thereof a potential level (voltage) which is essentially the same as one applied to the first input thereof; a circuitry input/output terminal being coupled to the first input of the first circuit means; second circuit means coupled to the first and second inputs of the first circuit means of sensing current drawn by the second load element and for generating an essentially identical current flow into a node coupled to the first input of the first circuit means and to the first load element; and the output of the first circuit means being coupled to the second input thereof through the second circuit means.