Method of fabricating a self aligned semiconductor device

Claim 1

A method of producing a self-aligned gate MESFET comprising the steps of: successively depositing a high melting point metallic film, a thin high melting point metal film, and an insulative film on a semiconductor substrate; anisotropically etching the superimposed films to form a gate structure including a metallic gate formed by the metallic layer, a dummy gate formed by the insulative layer, and a metal separator formed by the intermediate metal layer, protecting the metallic and insulative layers during the anisotropic etching step by the interposed metal layer selected to have an etching rate slower than the metallic or insulative layers; forming source and drain regions using the gate structure as a mask, said forming step including a high temperature annealing operation, the metal layer being sufficiently thin and the annealing temperature being sufficient to transform the metal layer to a metallic layer; forming a resist layer on the partly completed device leaving the upper surface of the dummy gate exposed; selectively etching the partly completed device to remove only the insulative layer thereby to expose the underlying metallic layer; and self-aligningly plating a low resistance metal layer of lower resistance than the high melting point metal layer on the exposed metallic layer to form a low resistance contact self-aligned on the high melting point gate.

Claim 2

A method of producing a self-aligned gate MESFET comprising the steps of: successively depositing a high melting point metallic film, a thin high melting point metal film, and an insulative film on a semiconductor substrate; anisotropically etching the superimposed films to form a gate structure including a metallic gate formed by the metallic layer, a dummy gate formed by the insulative layer, and a metal separator formed by the intermediate metal layer, protecting the metallic and insulative layers during the anisotropic etching step by the interposed metal layer selected to have an etching rate slower than the metallic or insulative layers; forming source and drain regions using the gate structure as a mask, said forming step including a high temperature annealing operation, the metal layer being sufficiently thin and the annealing temperature being sufficient to transform the metal layer to a metallic layer; forming a resist layer on the partly completed device leaving the upper surface of the dummy gate exposed; selectively etching the partly completed device to remove only the insulative layer thereby to expose the underlying metallic layer; and self-aligningly plating a low resistance metal layer of lower resistance than the high melting point metal layer on the exposed metallic layer to form a low resistance contact self-aligned on the high melting point gate.

Claim 10

A method of forming a semiconductor device having a metallic structure deposited on a substrate having both high temperature and low resistance properties, the method comprising the steps of: successively depositing three layers on the substrate, the lowermost layer comprising a high melting point metallic layer, the intermediate layer comprising a thin high melting point metal layer and the uppermost layer comprising an insulator layer, the etchant properties of the respective layers being selected so that the intermediate layer has a lower etching rate than the metallic layer or the insulator layer thereby to prevent undercutting of the superimposed layers; anisotropically etching the three superimposed layers using the intermediate high temperature metal layer to protect the metallic layer and insulator layer from undercutting thereby to form an aligned metallic structure precisely positioned on the semiconductor substrate; depositing a resist material over the partly completed device but leaving the upper surface of the insulator layer exposed; selectively etching the resist protected structure to remove the insulator layer thereby exposing the underlying metallic layer; and using said resist as a mask using a lift-off process to deposit a low resistance metal layer over the metallic layer in the area which had been occupied by the insulator layer, the low resistance metal layer having a resistance lower than that of the high melting point metal layer, thereby to accurately produce a self-aligned low resistance electrode over a high temperature metallic electrode.

Claim 11

A method of forming a semiconductor device having a metallic structure deposited on a substrate having both high temperature and low resistance properties, the method comprising the steps of: successively depositing three layers on the substrate, the lowermost layer comprising a high melting point metallic layer, the intermediate layer comprising a thin high melting point metal layer and the uppermost layer comprising an insulator layer, the etchant properties of the respective layers being selected so that the intermediate layer has a lower etching rate than the metallic layer or the insulator layer thereby to prevent undercutting of the superimposed layers; anisotropically etching the three superimposed layers using the intermediate high temperature metal layer to protect the metallic layer and insulator layer from undercutting thereby to form an aligned metallic structure precisely positioned on the semiconductor substrate; depositing a resist material over the partly completed device but leaving the upper surface of the insulator layer exposed; selectively etching the resist protected structure to remove the insulator layer thereby exposing the underlying metallic layer; and using said resist as a mask using a lift-off process to deposit a low resistance metal layer over the metallic layer in the area which had been occupied by the insulator layer, the low resistance metal layer having a resistance lower than that of the high melting point metal layer, thereby to accurately produce a self-aligned low resistance electrode over a high temperature metallic electrode.