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US4923822A
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US
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Method of fabricating a semiconductor device by capping a conductive layer with a nitride layer
Assignee: HP Inc
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Filing: 1989-05-22
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Granted: 1990-05-08
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Expires: 2009-05-22
Abstract
Abstract A method of fabricating a semiconductor device in an integrated circuit. A conductive titanium layer is deposited on a substrate in which source, drain and gate regions have been created. A titanium nitride layer is applied as a cap over the titanium layer. A first anneal at a relatively low temperature is performed, causing portions of the titanium which are adjacent the silicon surface to form a titanium-silicon compound and causing the remaining titanium and titanium nitride to form a nitride coating. This nitride coating is etched away and a final high-temperature anneal is performed, resulting in thick, smooth titanium silicide (TiSi 2 ) layers on the source and drain regions and gate pads.
Inventors
- 👤 Martin S. Wang
- 👤 Kuang-Yi Chiu
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 12:48
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/01; H10D30/021; H10D30/0212; H10D30/0223; H10D64/00; H10D64/01; H10D64/011; H10D64/0111; H10D64/0112; H10D64/013; H10D64/01302; H10D64/01304; H10D64/01306; H10D64/01308; H10D64/0131; Y; Y10; Y10S; Y10S257/00; Y10S257/90; Y10S257/915
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
146 words
A method of fabricating a semiconductor device, the method comprising: forming spaced-apart first and second field oxide regions in a planar surface of a substrate; creating a gate region between the field oxide regions; forming a source diffusion region between the gate region and the first field oxide region and a drain diffusion region between the gate region and the second field oxide region; covering the substrate with a conductive layer; covering the conductive layer with a nitride layer; annealing at a relatively low temperature whereby those portions of the conductive layer which overlie silicon react therewith to form a silicon compound and any remaining portions of the conductive layer react with the nitride layer to form a generally homogeneous nitride layer covering the device; etching to remove the nitride layer; and annealing at a relatively high temperature to convert the silicon compound into a silicide.
Claim 2
Independent Claim
146 words
A method of fabricating a semiconductor device, the method comprising: forming spaced-apart first and second field oxide regions in a planar surface of a substrate; creating a gate region between the field oxide regions; forming a source diffusion region between the gate region and the first field oxide region and a drain diffusion region between the gate region and the second field oxide region; covering the substrate with a conductive layer; covering the conductive layer with a nitride layer; annealing at a relatively low temperature whereby those portions of the conductive layer which overlie silicon react therewith to form a silicon compound and any remaining portions of the conductive layer react with the nitride layer to form a generally homogeneous nitride layer covering the device; etching to remove the nitride layer; and annealing at a relatively high temperature to convert the silicon compound into a silicide.
Claim 3
Dependent Claim
19 words
A method according to claim 1 wherein the conductive layer comprises titanium and the nitride layer comprises titanium nitride.
Claim 4
Dependent Claim
24 words
A method according to claim 2 wherein the titanium nitride coating is applied immediately after the titanium coating without any change in ambient atmosphere.
Claim 5
Dependent Claim
12 words
A method according to claim 1 wherein the etching comprises wet etching.
Claim 6
Dependent Claim
17 words
A method according to claim 4 wherein the wet etching is performed by means of sulfuric acid.
Claim 7
Dependent Claim
17 words
A method according to claim 4 wherein the wet etching is performed by means of ammonium hydroxide.
Claim 8
Dependent Claim
42 words
A method according to claim 1 wherein the step of creating a gate region comprises forming a gate oxide layer in the planar surface of the substrate and forming a silicon pad on the gate oxide layer to create the gate region.
Claim 9
Dependent Claim
48 words
A method according to claim 7 wherein the step of forming the diffusion regions comprises: coating the pad and the substrate with a dielectric layer; directionally etching the dielectric layer to provide oxide spacers around the pad; and performing ion implantation and drive-in to form the diffusion regions.
Claim 10
Dependent Claim
33 words
A method according to claim 7 wherein the step of forming the pad comprises forming a polysilicon layer over the gate oxide and then etching the polysilicon layer and the underlying gate oxide.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-05-07 | 1993-11-06 | 1994-05-08 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-05-07 | 1997-11-06 | 1998-05-08 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-05-07 | 2001-11-06 | 2002-05-08 | $7700.00 | Window Closed / Lapsed |