Error recovery scheme for destaging cache data in a multi-memory system

Claim 2

A data processing system, comprising: at least a first memory facility and a second memory facility; a processor connected to the memory facilities addressing data in the first memory facility and the second memory facility by a system address, wherein the processor includes: a cache for storing data staged from the memory facilities, including means for storing the system addresses of the data staged and means for storing indicators which identify the memory facilities from which the data is staged; means coupled to the cache for detecting errors in an indicator during a destaging operation; means coupled to the cache for destaging data and addresses to a memory facility identified by the corresponding indicator if no error in the indicator is detected; means coupled to the cache for destaging data and the corresponding system address to each of the memory facilities if an error is detected in a corresponding indicator; and the each of said memory facilities includes: means for receiving the system addresses and data destaged from the processor, including means for checking system addresses destaged from the processor to determine to which memory facility the corresponding destaged data belongs.

Claim 3

A system as in claim 1, wherein said receiving means in the memory facilities includes means for queuing destaged system addresses and data.

Claim 4

A system as in claim 1, wherein said indicator comprises a local/remote bit.

Claim 5

A system as in claim 3, including means for generating a first signal if the local/remote bit is at a first state and a second signal if the local/remote bit is at a second state.

Claim 6

A system as in claim 4, wherein said detecting means includes means for checking parity of the local/remote bit.

Claim 7

A system as in claim 5, wherein said generating means generates both the first and second signal if a parity error is detected by the parity checking means.

Claim 8

A system as in claim 1, wherein the address checking means includes a configuration table in a memory facility storing an identification of which memory facility corresponds to each system address.

Claim 9

A system as in claim 7, wherein a first memory facility discards destaged data if the identification in the configuration table corresponding to the destaged system address identifies a second memory facility.

Claim 10

A multiprocessor system, comprising: a first subsystem having a first processor connected to a first main memory facility; a second subsystem having a second processor connected to a second main memory facility; wherein the first main memory facility is connected to the second main memory facility; each of the first and second processors locating data in both the first and second main memory facilities by a system address, each processor having: a cache for storing data staged from the memory facilities, including means for storing system addresses of the staged data and means for storing indicators which identify the main memory facilities from which the data is staged; means responsive to said indicators for generating a first signal and a second signal to the corresponding memory facility; means coupled to the cache for detecting errors in an indicator during a destaging operation, including means for generating both the first and second signals if an error is detected; and means for destaging cache data and system addresses to the corresponding memory facility; each of the first and second memory facilities having: means for receiving the first and second signal from the corresponding processor, including means for transmitting a received second signal to the other memory facility; means for receiving addresses and data destaged from the corresponding processor concurrently with the first and second signal, including means for storing the data if the first signal is received and transmitting the data to the other memory facility if the second signal is received; means for receiving a second signal, addresses and data from the other memory facility, including means for storing the data if a second signal is received from the other memory facility.

Claim 11

A multiprocessor system, comprising: a first subsystem having a first processor connected to a first main memory facility; a second subsystem having a second processor connected to a second main memory facility; wherein the first main memory facility is connected to the second main memory facility; each of the first and second processors locating data in both the first and second main memory facilities by a system address, each processor having: a cache for storing data staged from the memory facilities, including means for storing system addresses of the staged data and means for storing indicators which identify the main memory facilities from which the data is staged; means responsive to said indicators for generating a first signal and a second signal to the corresponding memory facility; means coupled to the cache for detecting errors in an indicator during a destaging operation, including means for generating both the first and second signals if an error is detected; and means for destaging cache data and system addresses to the corresponding memory facility; each of the first and second memory facilities having: means for receiving the first and second signal from the corresponding processor, including means for transmitting a received second signal to the other memory facility; means for receiving addresses and data destaged from the corresponding processor concurrently with the first and second signal, including means for storing the data if the first signal is received and transmitting the data to the other memory facility if the second signal is received; means for receiving a second signal, addresses and data from the other memory facility, including means for storing the data if a second signal is received from the other memory facility.

Claim 12

A multiprocessor system as in claim 9, wherein said receiving means in each memory facility includes means for queuing the destaged address and data.

Claim 13

A multiprocessor system as in claim 9, wherein said indicator comprises a local/remote bit.

Claim 14

A multiprocessor system as in claim 11, wherein said errors are detected by means for checking parity of the local/remote bit.

Claim 15

A multiprocessor system as in claim 12, wherein said generating means generates both the first and second signal if a parity error is detected by the checking means.

Claim 16

A multiprocessor system as in claim 9, wherein each of the first and second main memory facilities includes: means, receiving the system addresses of destaged data, for checking the system addresses to determine to which of the first and second main memory facilities the corresponding destaged data belongs.

Claim 17

A multiprocessor system as in claim 14, wherein the address checking means includes a configuration table in each memory facility storing information identifying to which memory facility each system address belongs.

Claim 18

A multiprocessor system as in claim 15, wherein a main memory facility discards destaged data if the corresponding system address identifies a remote main memory facility.