TTL output driver gate configuration

Claim 2

A TTL output driver gate configuration which has reduced voltage spikes on internal power supply potential and ground potential nodes comprising: a P-channel pull-up transistor (P1) having a serpentine gate, a source and a drain, said pull-up transistor (P1) having a source coupled to a positive potential via the internal power supply potential node and its drain coupled to an output node, said serpentine gate of said pull-up transistor (P1) being formed of a first end and a second end; an N-channel pull-down transistor (N1) having a serpentine gate, a source and a drain, said pull-down transistor (N1) having its source coupled to a negative potential via the internal ground potential node and its drain coupled to the output node, said serpentine gate of said pull-down transistor (N1) being formed of a first end and a second end; first logic means (14) responsive to a data input signal making a low-to-high transition for generating a first control signal which is connected to the first gate end of said pull-up transistor; second logic means (16) responsive to the data input signal making a high-to-low transition for generating a second control signal which is connected to the first gate end of said pull-down transistor (N1); first positive feedback amplifier means (18) connected between the first and second gate ends of said pull-up transistor (N1) and being responsive to the first control signal for pulling down the second gate end of said pull-up transistor (P1) all the way to the negative potential so as to facilitate a low-to-high logic transition at the output node; and second positive feedback amplifier means (20) connected between the first and second gate ends of said pull-down transistor (N1) and being responsive to the second control signal for pulling up the second end of said pull-down transistor all the way to the positive potential so as to facilitate a high-to-low logic transition at the output node, whereby distributed R-C of the serpentine gates slow down the turn-on times of said pull-up and pull-down transistors (P1, N1) so as to reduce voltage spikes at the internal power supply potential and ground potential nodes during transitions at the output node.

Claim 3

A driver gate configuration as claimed in claim 1, wherein said first logic means comprises a first NAND logic gate (14).

Claim 4

A driver gate configuration as claimed in claim 1, wherein said second logic means comprises a first NOR logic gate (16).

Claim 5

A driver gate configuration as claimed in claim 1, wherein said pull-down transistor (N1) is quickly turned off for generating the low-to-high transition at the output node and wherein said pull-up transistor (P1) is initially turned on slowly so as to reduce the voltage spikes at the internal power supply node.

Claim 6

A driver gate configuration as claimed in claim 1, wherein said pull-up transistor (P1) is quickly turned off for generating the high-to-low transition at the output node and wherein said pull-down transistor (N1) is initially turned on slowly so as to reduce the voltage spikes at the internal ground node.

Claim 7

A driver gate configuration as claimed in claim 1, wherein said first positive feedback amplifier means comprises a second NOR logic gate (32) and a second N-channel transistor (N2).

Claim 8

A driver gate configuration as claimed in claim 6, wherein said second NOR logic gate (32) has one of its inputs connected to the first gate end of said pull-up transistor (P1) and its other input connected to the second gate end of said pull-up transistor (P1), said second N-channel transistor (N2) having its gate connected to the output of said second NOR gate (32), its drain connected to the second gate end of said pull-up transistor (P1), and its source connected to the ground potential node.

Claim 9

A driver gate configuration as claimed in claim 1, wherein said second positive feedback amplifier means comprises a second NAND logic gate (36) and a second P-channel transistor (P2).

Claim 10

A driver gate configuration as claimed in claim 8, wherein said second NAND gate (38) has one of its inputs connected to the first gate end of said pull-down transistor (N1) and its other input connected to the second gate end of said pull-down transistor (N1), said second P-channel transistor (P2) having its gate connected to the output of said second NAND gate (36), its drain connected to the second gate end of said pull-down transistor (N1), and its source connected to the internal power supply potential node.

Claim 11

A TTL output driver gate configuration which has reduced voltage spikes on internal power supply potential and ground potential nodes comprising: a P-channel pull-up transistor (P1) having a serpentine gate, a source and a drain, said pull-up transistor (P1) having a source coupled to a positive potential via the internal power supply potential node and its drain coupled to an output node, said serpentine gate of said pull-up transistor (P1) being formed of a first end and a second end; an N-channel pull-down transistor (N1) having a serpentine gate, a source and a drain, said pull-down transistor (N1) having its source coupled to a negative potential via the internal ground potential node and its drain coupled to the output node, said serpentine gate of said pull-down transistor (N1) being formed of a first end and a second end; a first NAND logic gate (14) responsive to a data input signal making a low-to-high transition for generating a first control signal which is connected to the first gate end of said pull-up transistor; a first NOR logic gate (16) responsive to the data input signal making a high-to-low transition for generating a second control signal which is connected to the first gate end of said pull-down transistor (N1); first positive feedback amplifier means (18) connected between the first and second gate ends of said pull-up transistor (N1) and being responsive to the first control signal for pulling down the second gate end of said pull-up transistor (P1) all the way to the negative potential so as to facilitate a low-to-high logic transition at the output node; and second positive feedback amplifier means (20) connected between the first and second gate ends of said pull-down transistor (N1) and being responsive to the second control signal for pulling up the second gate end of said pull-down transistor all the way to the positive potential so as to facilitate a high-to-low logic transition at the output node, whereby distributed R-C of the serpentine gates slow down the turn-on times of said pull-up and pull-down transistors (P1, N1) so as to reduce voltage spikes at the internal power supply potential and ground potential nodes during transitions at the output node.

Claim 12

A TTL output driver gate configuration which has reduced voltage spikes on internal power supply potential and ground potential nodes comprising: a P-channel pull-up transistor (P1) having a serpentine gate, a source and a drain, said pull-up transistor (P1) having a source coupled to a positive potential via the internal power supply potential node and its drain coupled to an output node, said serpentine gate of said pull-up transistor (P1) being formed of a first end and a second end; an N-channel pull-down transistor (N1) having a serpentine gate, a source and a drain, said pull-down transistor (N1) having its source coupled to a negative potential via the internal ground potential node and its drain coupled to the output node, said serpentine gate of said pull-down transistor (N1) being formed of a first end and a second end; a first NAND logic gate (14) responsive to a data input signal making a low-to-high transition for generating a first control signal which is connected to the first gate end of said pull-up transistor; a first NOR logic gate (16) responsive to the data input signal making a high-to-low transition for generating a second control signal which is connected to the first gate end of said pull-down transistor (N1); first positive feedback amplifier means (18) connected between the first and second gate ends of said pull-up transistor (N1) and being responsive to the first control signal for pulling down the second gate end of said pull-up transistor (P1) all the way to the negative potential so as to facilitate a low-to-high logic transition at the output node; and second positive feedback amplifier means (20) connected between the first and second gate ends of said pull-down transistor (N1) and being responsive to the second control signal for pulling up the second gate end of said pull-down transistor all the way to the positive potential so as to facilitate a high-to-low logic transition at the output node, whereby distributed R-C of the serpentine gates slow down the turn-on times of said pull-up and pull-down transistors (P1, N1) so as to reduce voltage spikes at the internal power supply potential and ground potential nodes during transitions at the output node.

Claim 13

A driver gate configuration as claimed in claim 10, wherein said pull-down transistor (N1) is quickly turned off for generating the low-to-high transition at the output node and wherein said pull-up transistor (P1) is initially turned on slowly so as to reduce the voltage spikes at the internal power supply node.

Claim 14

A driver gate configuration as claimed in claim 11, wherein said pull-up transistor (P1) is quickly turned off for generating the high-to-low transition at the output node and wherein said pull-down transistor (N1) is initially turned on slowly so as to reduce the voltage spikes at the internal ground node.

Claim 15

A driver gate configuration as claimed in claim 12, wherein said first positive feedback amplifier means comprises a second NOR logic gate (32) and a second N-channel transistor (N2).

Claim 16

A driver gate configuration as claimed in claim 13, wherein said second NOR logic gate (32) has one of its inputs connected to the first gate end of said pull-up transistor (P1) and its other input connected to the second gate end of said pull-up transistor (P1), said second N-channel transistor (N2) having its gate connected to the output of said second NOR gate (32), its drain connected to the second gate end of said pull-up transistor (P1), and its source connected to the ground potential node.

Claim 17

A driver gate configuration as claimed in claim 14, wherein said second positive feedback amplifier means comprises a second NAND logic gate (36) and a second P-channel transistor (P2).

Claim 18

A driver gate configuration as claimed in claim 15, wherein said second NAND gate (38) has one of its inputs connected to the first gate end of said pull-down transistor (N1) and its other input connected to the second gate end of said pull-down transistor (N1), said second P-channel transistor (P2) having its gate connected to the output of said second NAND gate (36), its drain connected to the second gate end of said pull-down transistor (N1), and its source connected to the internal power supply potential node.

Claim 19

A TTL output driver gate configuration which has reduced voltage spikes on an internal power supply potential node comprising: a P-channel pull-up transistor (P1) having a serpentine gate, a source and a drain, said pull-up transistor (P1) having its source coupled to a positive potential via the internal power supply potential node and its drain coupled to an output node, said serpentine gate of said pull-up transistor (P1) being formed of a first end and a second end; logic means responsive to a data input signal making a low-to-high transition for generating a control signal which is connected to the first gate end of said pull-up transistor (P1); and positive feedback amplifier means (18) connected between the first and second gate ends of said pull-up transistor (P1) and being responsive to the control signal for pulling down the second gate end of said pull-up transistor all the way to a negative supply potential so as to facilitate a low-to-high logic transition at the output node, whereby distributed R-C of the serpentine gate slows down the turn-on time of said pull-up transistor so as to reduce voltage spikes at the internal power supply potential node during transition at the output node.

Claim 20

A TTL output driver gate configuration which has reduced voltage spikes on an internal power supply potential node comprising: a P-channel pull-up transistor (P1) having a serpentine gate, a source and a drain, said pull-up transistor (P1) having its source coupled to a positive potential via the internal power supply potential node and its drain coupled to an output node, said serpentine gate of said pull-up transistor (P1) being formed of a first end and a second end; logic means responsive to a data input signal making a low-to-high transition for generating a control signal which is connected to the first gate end of said pull-up transistor (P1); and positive feedback amplifier means (18) connected between the first and second gate ends of said pull-up transistor (P1) and being responsive to the control signal for pulling down the second gate end of said pull-up transistor all the way to a negative supply potential so as to facilitate a low-to-high logic transition at the output node, whereby distributed R-C of the serpentine gate slows down the turn-on time of said pull-up transistor so as to reduce voltage spikes at the internal power supply potential node during transition at the output node.

Claim 21

A driver gate configuration as claimed in claim 17, wherein said logic means comprises a first NAND logic gate (14).

Claim 22

A driver gate configuration as claimed in claim 18, wherein said positive feedback amplifier means comprises a NOR logic gate (32) and an N-channel transistor (N2).

Claim 23

A driver gate configuration as claimed in claim 19, wherein said NOR logic gate (32) has one of its inputs connected to the first gate end of said pull-up transistor (P1) and its other input connected to the second gate end of said pull-up transistor (P1), said N-channel transistor (N2) having its gate connected to the output of said NOR gate (32), its drain connected to the second gate end of said pull-up transistor (P1), and its source connected to a ground potential node.