US4918331A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Logic circuits with data resynchronization
Assignee: US Philips Corp
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Filing: 1989-05-26
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Granted: 1990-04-17
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Expires: 2009-05-26
Abstract
Abstract In relatively large systems of (integrated) circuits, data signals can experience a delay which is in the order of magnitude of a clock-pulse period. The receiving circuit (i.e. receiving the data signal) then receives the data signal too late (the clock pulse has ceased) and can at that moment no longer take over the data signal for further processing or transport. In the system according to the invention the clock pulses are led via a delaying element (for example, the inverting circuits in series) to the receiving circuit (slave of the master/slave flip-flop). The data output of the receiving circuit is connected to a data input of another circuit (master of another master/slave flip-flop), which receives the undelayed clock pulses, the data delay between the receiving circuit and the other circuit being negligible. The data delay is thus distributed over two clock pulses.
Inventors
- 👤 Adrianus T. Van Zanten
- 👤 Hendrikus J. M. Veendrick
- 👤 Leonardus C. M. G. Pfennings
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 05:00
CPC Classifications
H; H03; H03K; H03K3/00; H03K3/02; H03K3/027; H03K3/037; H03K3/0372; H03K19/00; H03K19/003; H03K19/00323
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
148 words
A system of logic circuits comprising at least a first circuit and a second circuit, a data line for transferring a logic signal from said first circuit to said second circuit, and a clock line for providing a clock signal having clock pulses to said first circuit to control the transfer of the logic signal, said data line and said clock line each causing a delay in transmission of logic signals and clock pulses, respectively, and a delaying element for providing delayed clock pulses to said second circuit, wherein the total logic signal delay between said first circuit and said second circuit caused by at least one of geometrical distance and intervening circuit elements is less than the sum of the duration of a clock pulse period and the delay time of said delaying element and said first circuit and said second circuit each comprise a bistable circuit.
Claim 2
Independent Claim
148 words
A system of logic circuits comprising at least a first circuit and a second circuit, a data line for transferring a logic signal from said first circuit to said second circuit, and a clock line for providing a clock signal having clock pulses to said first circuit to control the transfer of the logic signal, said data line and said clock line each causing a delay in transmission of logic signals and clock pulses, respectively, and a delaying element for providing delayed clock pulses to said second circuit, wherein the total logic signal delay between said first circuit and said second circuit caused by at least one of geometrical distance and intervening circuit elements is less than the sum of the duration of a clock pulse period and the delay time of said delaying element and said first circuit and said second circuit each comprise a bistable circuit.
Claim 3
Dependent Claim
59 words
A system as claimed in claim 1, characterized in that the first and second bistable circuits comprise, respectively, the master and slave of a master/slave flip-flop, the delay time and a signal take-over time of the slave together being smaller than said sum of the duration of a clock pulse period and the delay time of said delaying element.
Claim 4
Dependent Claim
128 words
A system as claimed in claim 1, characterized in that the first and second bistable circuits comprise at least first and second master/slave flip-flop (FF) circuits, in which a logic signal from the first master/slave flip-flop circuit comprising a transmitting master/slave FF circuit is provided to the second master/slave flip-flop circuit comprising a receiving master/slave FF circuit, under the control of said clock signal which is provided to the masters of the master/slave FF circuits and via said delaying elements to the slaves of the master/slave FF circuits, the slave of the transmitting FF circuit located adjacent the master of the receiving FF circuit being integrated so that a delay of the signal from the transmitting slave to the receiving master is essentially smaller than the clock-pulse duration.
Claim 5
Dependent Claim
76 words
A system as claimed in claim 1, 2 or 3, further comprising a third circuit, characterized in that the sum of the delay time of the delaying element and a signal take-over time of said third circuit connected to an output of the second circuit, which third circuit comprises a master flip-flop (FF) and takes over the logic signal under the control of clock pulses, is at most equal to the duration of said clock signal.
Claim 6
Dependent Claim
25 words
A system as claimed in claim 1, 2 or 3, characterized in that the delaying element comprises at least two inverting circuits connected in series.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-04-16 | 1993-10-16 | 1994-04-17 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-04-16 | 1997-10-16 | 1998-04-17 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-04-16 | 2001-10-16 | 2002-04-17 | $7700.00 | Window Closed / Lapsed |