US4916654A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method for transfer of data via a window buffer from a bit-planar memory to a selected position in a target memory
Assignee: International Business Machines Corp
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Filing: 1988-09-06
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Granted: 1990-04-10
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Expires: 2008-09-06
Abstract
Abstract A graphic display PC/interface system is described which includes three memory units: a source memory which is addressed in planar byte increments and stores display data units on a bit per plane basis; a target memory for storing display data units in a manner suitable for operation of a display unit; and a window buffer for transferring display data unit from the source memory to the target memory. The system transfers a quantity of display data unit bytes from the source memory to the target memory by accessing pairs of planar bytes, which pair of planar bytes may have a display data unit byte bridging therebetween. The method comprises selecting a first pair of planar bytes from the source memory; aligning the display data unit byte which lies totally within the selected first pair of planar bytes; selecting a second pair of planar bytes from the source memory; aligning a display data unit byte which lies totally within the second selected pair of planar bytes; consolidating the display data unit byte which bridges between the first and second pairs of selected planar bytes; aligning the consolidated display data unit byte; and transferring aligned display data unit bytes to the window buffer.
Inventors
- 👤 Arthur M. Sherman
- 👤 Peter C. Yanker
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 14:57
CPC Classifications
G; G09; G09G; G09G5/00; G09G5/36; G09G5/14
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
209 words
In a system comprising a source memory which includes a plurality of bit planes addressable in planar data units, display data units being stored therein on a bit-plane basis; a target memory for storing display data units; window buffer means interposed between said source memory and said target memory; and means for transforming preset data lengths of display data units from bit-planes in said source memory, via said window buffer, to said target memory, wherein a preset data length of said display data units may start at any planar data unit bit position and may bridge between adjacent planar data units, the method comprising: selecting and aligning a first preset data length of display data unit bits which resides in a first pair of planar data units in said source memory; selecting and aligning a second preset data length of display data unit bits which resides in a second pair of planar data units in said source memory; consolidating a third preset data length of display data unit bits which bridges between said first and second pairs of planar data units; aligning said consolidated third preset data length of display data unit bits; and transferring said aligned data lengths of display data unit bits to said window buffer means.
Claim 2
Dependent Claim
209 words
In a system comprising a source memory which includes a plurality of bit planes addressable in planar data units, display data units being stored therein on a bit-plane basis; a target memory for storing display data units; window buffer means interposed between said source memory and said target memory; and means for transforming preset data lengths of display data units from bit-planes in said source memory, via said window buffer, to said target memory, wherein a preset data length of said display data units may start at any planar data unit bit position and may bridge between adjacent planar data units, the method comprising: selecting and aligning a first preset data length of display data unit bits which resides in a first pair of planar data units in said source memory; selecting and aligning a second preset data length of display data unit bits which resides in a second pair of planar data units in said source memory; consolidating a third preset data length of display data unit bits which bridges between said first and second pairs of planar data units; aligning said consolidated third preset data length of display data unit bits; and transferring said aligned data lengths of display data unit bits to said window buffer means.
Claim 3
Dependent Claim
33 words
The system as defined in claim 1 wherein said first selecting and aligning step includes the step of rotating said first preset data length of display data unit bits to a preset boundary.
Claim 4
Dependent Claim
33 words
The system as defined in claim 2 wherein said second selecting and aligning step includes the step of rotating said second preset data length of display data unit bits to a preset boundary.
Claim 5
Dependent Claim
28 words
The system as defined in claim 3 wherein said transferring step first transfers said first preset data length of display data unit bits to said window buffer means.
Claim 6
Dependent Claim
64 words
The system as defined in claim 4 wherein said consolidating step further includes the step of moving a portion of said third preset data length of display data unit bits which is part of said second pair of planar data units into juxtaposition with a portion of said third display data unit bits which is part of said first pair of planar data units.
Claim 7
Dependent Claim
33 words
The system as defined in claim 5 wherein said consolidating step includes a masking step to assure proper ordering of the bits of said third preset data length of display data unit bits.
Claim 8
Dependent Claim
38 words
The system as defined in claim 6 wherein said transferring step, after the transfer of said first preset data length of display data unit bits, transfers said third consolidated display data unit bits to said window buffer means.
Claim 9
Dependent Claim
180 words
In a system for transferring bytes of display data bits from a bit-planar, byte organized source memory through a window buffer to a target memory, said system including first and second double byte register means, the method comprising: loading into said first register means a first pair of bytes from a bit-plane of said source memory, said first pair of bytes including a byte of display data bits and a partial byte of display data bits; aligning said byte of display data bits in said first register means; loading into said second register means, a second pair of bytes from a bit-plane of said source memory, said second pair of bytes including a byte of display data bits and a partial byte of display data bits; aligning said byte of said display data bits in said second register means; consolidating said partial bytes of display data bits from said first and second register means into a consolidated byte and aligning said consolidated byte; whereby said aligned bytes of display data bits may be transferred in alignment to said window buffer.
Claim 10
Dependent Claim
180 words
In a system for transferring bytes of display data bits from a bit-planar, byte organized source memory through a window buffer to a target memory, said system including first and second double byte register means, the method comprising: loading into said first register means a first pair of bytes from a bit-plane of said source memory, said first pair of bytes including a byte of display data bits and a partial byte of display data bits; aligning said byte of display data bits in said first register means; loading into said second register means, a second pair of bytes from a bit-plane of said source memory, said second pair of bytes including a byte of display data bits and a partial byte of display data bits; aligning said byte of said display data bits in said second register means; consolidating said partial bytes of display data bits from said first and second register means into a consolidated byte and aligning said consolidated byte; whereby said aligned bytes of display data bits may be transferred in alignment to said window buffer.
Claim 11
Dependent Claim
55 words
The system as defined in claim 8 further including the step of transferring one of said aligned bytes of display data unit bits from a register means to said window buffer, said consolidating step further including the step of transferring said partial bytes of display data unit bits into juxtaposition in one said register means.
Claim 12
Dependent Claim
26 words
The system as defined in claim 9 wherein said transfer step takes place through a mask which negates all bits not included in said partial bytes.
Claim 13
Dependent Claim
30 words
The system as in claim 10 further including the steps of Or'ing said partial bytes together to accomplish said consolidation and subsequently transferring said consolidated byte to said window buffer.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-04-09 | 1993-10-09 | 1994-04-10 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-04-09 | 1997-10-09 | 1998-04-10 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-04-09 | 2001-10-09 | 2002-04-10 | $7700.00 | Window Closed / Lapsed |