Electronic postage meter having redundant memory

Claim 2

In an electronic postage meter system having a microprocessor connected to a plurality of address lines, a plurality of data lines, and control line means, and random access memory means connected to said address and data lines and to said control line means to enable storage of data in said random access memory means and reading of data from said random access memory means under control of said microprocessor; the improvement wherein said random access memory means comprises first and second random access memories each connected to separate groups of said address lines and separate groups of said data lines, whereby data may be transferred to and from said first and second random access memories independently of any common interconnection.

Claim 3

The electronic postage meter system of claim 1 further comprising permanent memory means for storing postage meter routines for controlling said microprocessor, said routines addressing said first and second random access memories time sequentially for transfer of identical data thereto.

Claim 4

The electronic postage meter system of claim 1 further comprising permanent memory means having postage meter programs for controlling said microprocessor, said programs addressing said first and second random access memories with time overlap, to transfer identical data to and from said first and second random access memories respectively whereby the identical data is transferred to and from said first and second random access memories at different times while both of said random access memories are addressed in a plurality of successive addressing cycles of said microprocessor and different data is transferred to and from said first and second random access memories at a common time when both random access memories are accessed.

Claim 5

The electronic postage meter system of claim 1 wherein said microprocessor has first and second coding/decoding means for coding data applied to and decoding data retrieved from said first and second random access memories, respectively via said separate groups of data lines, said first and second coding/decoding means having different coding whereby data is stored in a different form in said first and second random access memories.

Claim 6

In an electronic postage meter system having a microprocessor with a plurality of address lines a plurality of data lines, and control line means, and random access memory means connected to said address and data lines and control line means to enable transfer of data between said random access memory means and microprocessor, said postage meter having a printer connected to be controlled by said microprocessor, and feedback means for signalling the setting of the printing means to the microprocessor; the improvement wherein said random access memory means comprises first and second random access memories, and a control means connected to said first and second random access memories and to said feedback means, said control means being responsive to feedback from said feedback means to update independently the accounting data in each of said first and second random access memories.

Claim 7

In an electronic postage meter system having a microprocessor with a plurality of address lines a plurality of data lines, and control line means, and random access memory means connected to said address and data lines and control line means to enable transfer of data between said random access memory means and microprocessor, said postage meter having a printer connected to be controlled by said microprocessor, and feedback means for signalling the setting of the printing means to the microprocessor; the improvement wherein said random access memory means comprises first and second random access memories, and a control means connected to said first and second random access memories and to said feedback means, said control means being responsive to feedback from said feedback means to update independently the accounting data in each of said first and second random access memories.

Claim 8

In an electronic postage meter having a printing unit and an accounting unit connected to said printing unit for accounting for the printing of postage; the improvement wherein said postage meter accounting unit comprises first and second microprocessors, said first and second microprocessors having programs for separately updating their respective accounting registers, to account for the printing of postage by said meter, and means for comparing the accounting results in said first and second accounting registers for disabling said postage meter in the absence of a proper comparison.

Claim 9

In an electronic postage meter having a printing unit and an accounting unit connected to said printing unit for accounting for the printing of postage; the improvement wherein said postage meter accounting unit comprises first and second microprocessors, said first and second microprocessors having programs for separately updating their respective accounting registers, to account for the printing of postage by said meter, and means for comparing the accounting results in said first and second accounting registers for disabling said postage meter in the absence of a proper comparison.

Claim 10

The electronic postage meter of claim 6 wherein said printing unit comprises a further microprocessor having a postage printing program for controlling printing of said postage meter.

Claim 11

A microprocessor system including an address bus having a plurality of address lines, a data bus having a plurality of data lines, and a control bus having a plurality of control lines, a microprocessor connected to each of the address lines and data lines respectively of said address and data buses, and coupled to said control bus, first and second random access memories, each being connected to different lines of said address bus and different lines of said data bus, whereby said first and second random access memories may be separately addressed.

Claim 12

A microprocessor system including an address bus having a plurality of address lines, a data bus having a plurality of data lines, and a control bus having a plurality of control lines, a microprocessor connected to each of the address lines and data lines respectively of said address and data buses, and coupled to said control bus, first and second random access memories, each being connected to different lines of said address bus and different lines of said data bus, whereby said first and second random access memories may be separately addressed.

Claim 13

The microprocessor system of claim 8 wherein said microprocessor has first and second coding/decoding means for coding data applied to and decoding data retrieved from said first and second random access memories, respectively via said different lines of said data bus, said first and second coding/decoding means having different coding whereby data is stored in a different form in said first and second random access memories.

Claim 14

The microprocessor system of claim 8 further including a program memory for controlling the operation of said microprocessor and having a program for addressing said first and second random access memories to store the same data therein during different time intervals.

Claim 15

The microprocessor system of claim 10 wherein said program addresses corresponding storage locations of said first and second random access memories, wherein corresponding data is stored in or read therefrom at different times.

Claim 16

The microprocessor system of claim 11 wherein said program simultaneously stores different data in said first and second random access memories at noncorresponding address locations.

Claim 17

The microprocessor system of claim 8 wherein said first and second random access memories are nonvolatile memories.

Claim 18

The microprocessor system of claim 13 further comprising means responsive to differences in data stored in first and second random access memories for disabling further operation of said microprocessor.

Claim 19

In an electronic postage meter system having a microprocessor connected to a plurality of address lines, a plurality of data lines, and control line means, and random access memory means connected to said address and data lines and to said control line means to enable writing of data into said random access memory means and reading of data stored in said random access memory means under control of said microprocessor; the improvement wherein: said random access memory means comprises first and second separate and independent random access memories, said plurality of address lines comprises first and second entirely separate groups of address lines, said plurality of data lines comprises first and second entirely separate groups of data lines, said first random access memory is connected only to the first of said first and second groups of address and data lines of said plurality of address and data lines, and said second random access memory is connected only to the second of said first and second groups of address and data lines of said plurality of address and data lines, whereby data may be stored into and read from said first and second random access memories independently of any common interconnection.

Claim 20

In an electronic postage meter system having a microprocessor connected to a plurality of address lines, a plurality of data lines, and control line means, and random access memory means connected to said address and data lines and to said control line means to enable writing of data into said random access memory means and reading of data stored in said random access memory means under control of said microprocessor; the improvement wherein: said random access memory means comprises first and second separate and independent random access memories, said plurality of address lines comprises first and second entirely separate groups of address lines, said plurality of data lines comprises first and second entirely separate groups of data lines, said first random access memory is connected only to the first of said first and second groups of address and data lines of said plurality of address and data lines, and said second random access memory is connected only to the second of said first and second groups of address and data lines of said plurality of address and data lines, whereby data may be stored into and read from said first and second random access memories independently of any common interconnection.

Claim 21

A microprocessor system having a microprocessor connected to a plurality of address lines, a plurality of data lines, and control lines means, and random access memory means connected to said address and data lines and to said control line means to enable writing of data into said random access memory means and reading of data stored in said random access memory means under control of said microprocessor; the improvement wherein: said random access memory means comprises first and second separate and independent random access memories, said plurality of address lines comprises first and second entirely separate groups of address lines, said plurality of data lines comprises first and second entirely separate groups of data lines, said first random access memory is connected only to the first of said first and second groups of address and data lines of said plurality of address and data lines, and said second random access memory is connected only to the second of said first and second groups of address and data lines of said plurality of address and data lines, whereby data may be stored into and read from said first and second random access memories independently of any common interconnection.

Claim 22

A microprocessor system having a microprocessor connected to a plurality of address lines, a plurality of data lines, and control lines means, and random access memory means connected to said address and data lines and to said control line means to enable writing of data into said random access memory means and reading of data stored in said random access memory means under control of said microprocessor; the improvement wherein: said random access memory means comprises first and second separate and independent random access memories, said plurality of address lines comprises first and second entirely separate groups of address lines, said plurality of data lines comprises first and second entirely separate groups of data lines, said first random access memory is connected only to the first of said first and second groups of address and data lines of said plurality of address and data lines, and said second random access memory is connected only to the second of said first and second groups of address and data lines of said plurality of address and data lines, whereby data may be stored into and read from said first and second random access memories independently of any common interconnection.