Microcode control system in a microcomputer capable of branching to different microcode routines

Claim 1

Apparatus for use in a microcomputer operable under microcode control for controlling the branching of microcode sequences, said microcomputer including a memory for storing microcode and a branch controller responsive to a clock signal for issuing an address signal to said memory for specifying the address of microcode to be executed, said memory providing a branch control signal to said branch controller indicating the presence or absence of branch instructions in said microcode sequences, said apparatus being characterized in that: said branch controller is structured and arranged to provide a provisional address to said memory in a first clock period for the next sequential code in a microcode sequence assuming no branch is indicated, said address being provided prior to determining the presence of a branch instruction; said branch controller includes branch information incorporation means for incorporating branch information into said provisional address, said incorporation means being structured and arranged to change the provisionally provided address, in a subsequent clock period, to reflect the address of the next microcode in a branched sequence whenever said branch control signal indicates a branch instruction is present; and said branch control means provides said changed address to said memory in said same subsequent clock period.

Claim 4

A method of controlling the branching of microcode sequences in a microcomputer under microcode control, said microcomputer including a memory for storing microcode and a branch controller for issuing an address signal to said memory for specifying the address of microcode to be executed, said method comprising the steps of: in a first clock period, provisionally providing to said memory the next sequential address in a microcode sequence assuming no branch is indicated said address being provided prior to determining the presence of a branch instruction; in a subsequent clock period, changing the provisionally provided address, if a branch instruction is determined to be present responsive to a branch control signal, to indicate the address of the next microcode in the branched sequence, and in said same subsequent clock period providing said changed address for said memory.

Claim 5

A method of controlling the branching of microcode sequences in a microcomputer under microcode control, said microcomputer including a memory for storing microcode and a branch controller for issuing an address signal to said memory for specifying the address of microcode to be executed, said method comprising the steps of: in a first clock period, provisionally providing to said memory the next sequential address in a microcode sequence assuming no branch is indicated said address being provided prior to determining the presence of a branch instruction; in a subsequent clock period, changing the provisionally provided address, if a branch instruction is determined to be present responsive to a branch control signal, to indicate the address of the next microcode in the branched sequence, and in said same subsequent clock period providing said changed address for said memory.