Picture processor

Claim 2

A picture processor comprising: a memory array for storing video data involving at least one picture frame; and line buffer memory means for processing at a high rate video signals included in one scan line of the picture frame; said line buffer memory means including a read line buffer memory operatively connected to said memory array, and a write line buffer memory operatively connected to said memory array.

Claim 3

A picture processor as set forth in claim 1 wherein said memory array comprises a field memory array for storing video data involving at least one picture frame; and wherein said line buffer memory means is capable of asynchronously writing and reading video data included in one scan line of a picture frame; and further including a circuit section for receiving external signals and generating sequentially internal addresses.

Claim 4

A picture processor as set forth in claim 1 wherein said memory array comprises a frame memory array.

Claim 5

A picture processor as set forth in claim 1 wherein said read line buffer memory is selectively usable as a read-only read line buffer memory.

Claim 6

A picture processor as set forth in claim 4 wherein the write line buffer memory is capable of writing video data included in one scan line asynchronously with the timing of video data readout by said read line buffer memory.

Claim 7

A picture processor as set forth in claim 1 wherein said read line buffer memory is capable of reading at a twice-higher rate than the writing rate of the write line buffer memory.

Claim 8

A picture processor as set forth in claim 6 wherein the write line buffer memory is capable of sequentially writing video data per scan line synchronously with picture processing signals for a video display; and the read line buffer memory is capable of reading data written by said write line buffer memory under conversion from interlaced to non-interlace scanning; and further including a circuit section for receiving external signals and generating sequentially internal addresses to control said memory array and said write and read lie buffer memories.

Claim 9

A picture processor comprising: a memory array for storing video data including at least one picture frame; a first buffer memory operatively connected to the memory array; a second buffer memory operatively connected to the first buffer memory and the memory array; interface means for transferring serial video data to said memory array and operatively connected to said first and second buffer memories; and control circuit means operatively connected to said interface means, the memory array, the first buffer memory and the second buffer memory for regulating the transfer of video data into and out of said memory array via said first and second buffer memories.

Claim 10

A picture processor comprising: a memory array for storing video data including at least one picture frame; a first buffer memory operatively connected to the memory array; a second buffer memory operatively connected to the first buffer memory and the memory array; interface means for transferring serial video data to said memory array and operatively connected to said first and second buffer memories; and control circuit means operatively connected to said interface means, the memory array, the first buffer memory and the second buffer memory for regulating the transfer of video data into and out of said memory array via said first and second buffer memories.

Claim 11

A picture processor as set forth in claim 8 wherein said first buffer memory comprises: a first memory having a predetermined number of storage locations, and a first location pointer operatively connected between said interface means and the predetermined number of storage locations of the first memory.

Claim 12

A picture processor as set forth in claim 9 wherein said second buffer memory comprises: a second memory having a predetermined number of storage locations, and a second location pointer operatively connected between said interface means and the predetermined number of storage locations of the second memory.

Claim 13

A picture processor as set forth in claim 10 wherein said interface means comprises an input terminal and an output terminal.

Claim 14

A picture processor as set forth in claim 11 wherein said interface means further includes a switching circuit operatively arranged to selectively connect the input terminal to the first location pointer and to the second location pointer.

Claim 15

A picture processor as set forth in claim 11 wherein said interface means further includes a switching circuit operatively arranged to selectively connect the output terminal to the first location pointer and to the second location pointer.

Claim 16

A picture processor comprising: a memory array for storing picture data; a first buffer memory for buffering of video data in parallel arrangement to the memory array; a second buffer memory for buffering of video data in parallel arrangement to the memory array and the first buffer memory; interface means for transferring serial video data to said memory array and operatively connected to said first and second buffer memories; and control circuit means operatively connected to said interface means, the memory array, the first buffer memory and the second buffer memory for controlling the buffering of the parallel video data and interfacing of the serial video data.

Claim 17

A picture processor comprising: a memory array for storing picture data; a first buffer memory for buffering of video data in parallel arrangement to the memory array; a second buffer memory for buffering of video data in parallel arrangement to the memory array and the first buffer memory; interface means for transferring serial video data to said memory array and operatively connected to said first and second buffer memories; and control circuit means operatively connected to said interface means, the memory array, the first buffer memory and the second buffer memory for controlling the buffering of the parallel video data and interfacing of the serial video data.

Claim 18

A picture processor as set forth in claim 14 wherein said first buffer memory comprises: a first memory having a predetermined number of storage locations for storing the data in parallel arrangement with the memory array, and a first location pointer operatively connected between said interface means and the predetermined number of storage locations of the first memory for serially transferring data between the first memory and the interface means.

Claim 19

A picture processor as set forth in claim 15 wherein said second buffer memory comprises: a second memory having a predetermined number of storage locations for storing data in parallel arrangement with the memory array, and a second location pointer operatively connected between said interface means and the predetermined number of storage locations of the second memory for serially transferring data between the interface means and the second memory.

Claim 20

A picture processor as set forth in claim 16 wherein said interface means comprises an input terminal for applying serial data to the memory array and an output terminal for receiving serial data from the memory array.

Claim 21

A picture processor as set forth in claim 17 wherein said interface means further includes a switching circuit operatively arranged for selectively connecting the input terminal to the first location pointer and to the second location pointer.

Claim 22

A picture processor as set forth in claim 17 wherein said interface means further includes a switching circuit operatively arranged for selectively connecting the output terminal to the first location pointer and to the second location pointer.

Claim 25

A method as set forth in claim 20 wherein buffering data in the first buffer memory comprises: storing data in a first memory having a predetermined number of storage locations, and serially transferring data between the interface section and storage locations within the first memory with a first location pointer.

Claim 26

A method as set forth in claim 21 wherein buffering data in the second buffer memory comprises: storing data in a second memory having a predetermined number of storage locations, and serially transferring data between the interface section and storage locations within the second memory with a second location pointer.

Claim 27

A method as set forth in claim 22 wherein serially transferring data between the interface section and storage locations within the first memory includes selectively connecting an input terminal of the interface section to the first location pointer.

Claim 28

A method as set forth in claim 23 wherein serially transferring data between the interface section and storage locations within the first memory includes selectively connecting an output terminal of the interface section to the first location pointer.

Claim 29

A method as set forth in claim 24 wherein serially transferring data between the interface section and storage locations within the second memory includes selectively connecting an input terminal of the interface section to the second location pointer.

Claim 30

A method as set forth in claim 25 wherein serially transferring data between the interface section and storage locations within the second memory includes selectively connecting an output terminal of the interface section to the second location pointer.

Claim 31

A picture processor comprising: a memory array for storing video data involving at least one picture frame; buffer memory means including a read line buffer memory means, and a write line buffer memory means; said read line buffer memory means being operatively connected to said memory array and being alternatively switchable between a first state in which said read line buffer memory means serves as a line buffer memory for processing at a high rate video signals included in one scan line of the picture frame storable in said memory array and a second state in which said read line buffer memory means serves as a read-only line buffer memory, and said write line buffer memory means being operatively connected to said memory array and to said read line buffer memory means for writing video data included in one scan line of said picture frame asynchronously with the timing of data read out by said read line buffer memory means when serving as said read-only line buffer memory.

Claim 32

A picture processor comprising: a memory array for storing video data involving at least one picture frame; buffer memory means including a read line buffer memory means, and a write line buffer memory means; said read line buffer memory means being operatively connected to said memory array and being alternatively switchable between a first state in which said read line buffer memory means serves as a line buffer memory for processing at a high rate video signals included in one scan line of the picture frame storable in said memory array and a second state in which said read line buffer memory means serves as a read-only line buffer memory, and said write line buffer memory means being operatively connected to said memory array and to said read line buffer memory means for writing video data included in one scan line of said picture frame asynchronously with the timing of data read out by said read line buffer memory means when serving as said read-only line buffer memory.

Claim 33

A picture processor comprising: a memory array for storing video data involving at least one picture frame; and line buffer memory means for processing at a high rate video signals included in one scan line of said picture frame, said line buffer memory means including a write-only line buffer memory section and a read line buffer memory section capable of reading data at a rate twice that of the writing rate of said write-only line buffer memory section.

Claim 34

A picture processor comprising: a memory array for storing video data involving at least one picture frame; and line buffer memory means for processing at a high rate video signals included in one scan line of said picture frame, said line buffer memory means including a write-only line buffer memory section and a read line buffer memory section capable of reading data at a rate twice that of the writing rate of said write-only line buffer memory section.

Claim 35

A picture processor as set forth in claim 28, wherein said write-only line buffer memory section is a write line buffer memory for sequentially writing video data per scan line synchronously with picture processing signals for a video display, said read line buffer memory section is a read line buffer memory having the capability of reading data written by said write line buffer memory undergoing conversion from interlace to non-interlace scanning; and circuit section means for receiving external signals and generating sequentially internal addresses to control said memory array and said write and read line buffer memories; and said write and read line buffer memories and said circuit section means being provided on a single integrated circuit chip.