← Back to Patent Explorer
US4916084A Expired / Lapsed US ⏱️ 0.0 years remaining

Method for manufacturing MOS semiconductor devices

Assignee: Toshiba Corp
•
Filing: 1988-07-12
•
Granted: 1990-04-10
•
Expires: 2008-07-12
📄 Original PDF 🌐 Google Patents 🔄 Sync Now

Abstract

Abstract A method for manufacturing MOS semiconductor devices comprises the steps of forming a oxidation resistant film on the upper and side surfaces of a gate electrode which is formed on a silicon substrate via an oxide film and whose upper and side surfaces are coated with an insulation oxide film, effecting thermal oxidation with the oxidation resistant film as a mask, removing the oxidation resistant film and the oxide film lying directly under the oxidation resistant film to expose the surface of the substrate, doping impurity into the exposed surface area of the substrate to form impurity regions, forming a silicon layer on the exposed surface of the substrate by a growth process, forming a first refractory metal layer on the entire surface of the structure, forming an insulation film on the first refractory metal layer, selectively removing the insulation film to form a contact hole, forming a second refractory metal layer in the contact hole by a deposition process, removing the insulation film and the first refractory metal layer except that part thereof which lies directly under the second refractory metal layer, depositiong an interlayer insulation film on the entire surface of the structure, planarizing the surface of the interlayer insulation film and then etching back the interlayer insulation film to expose the surface of the second refractory metal layer, and forming a metal wiring layer on the exposed surface of the second refractory metal layer.

Inventors

  • 👤 Hideki Shibata
  • 👤 Mitsuchika Saitoh

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-31 10:57
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/01; H10D30/021; H10D30/027; H10D30/0275; H10D62/00; H10D62/10; H10D62/13; H10D62/149; H10D62/17; H10D62/351; H10D62/357; H10P; H10P14/00; H10P14/60; H10P14/61; H10P14/63; H10P14/6326; H10P14/6349; H10P76/00; H10P76/40; H10W; H10W20/00; H10W20/01; H10W20/031; H10W20/063; H10W20/069; Y; Y10; Y10S; Y10S438/00; Y10S438/975

Claims Analysis

Total Claims: 8
Claim 1
Independent Claim 232 words
A method for manufacturing MOS semiconductor devices which comprises the steps of: forming an oxidation resistant film on the upper and side surfaces of a gate electrode which is formed on a semiconductor substrate via an oxide film and whose upper and side surfaces are coated with an insulation oxide film; effecting thermal oxidation with said oxidation resistant film as a mask; removing said oxidation resistant film and part of said oxide film lying directly under said oxidation resistant film to selectively expose the surface of said semiconductor substrate; doping impurity into the exposed surface area of said semiconductor substrate to form impurity regions serving as source and drain regions; forming a semiconductor layer on the exposed surface of said semiconductor substrate by a growth process; forming a first refractory metal layer on the entire surface of the semiconductor structure; forming an insulation film on said first refractory metal layer; selectively removing said insulation film to form at least one contact hole; forming a second refractory metal layer in said contact hole by a deposition process; removing said insulation film and said first refractory metal layer except that part thereof which lies directly under said second refractory metal layer; and depositing an interlayer insulation film on the entire surface of the semiconductor structure, and planarizing the surface of said interlayer insulation film to expose the surface of said second refractory metal layer.
Claim 2
Independent Claim 232 words
A method for manufacturing MOS semiconductor devices which comprises the steps of: forming an oxidation resistant film on the upper and side surfaces of a gate electrode which is formed on a semiconductor substrate via an oxide film and whose upper and side surfaces are coated with an insulation oxide film; effecting thermal oxidation with said oxidation resistant film as a mask; removing said oxidation resistant film and part of said oxide film lying directly under said oxidation resistant film to selectively expose the surface of said semiconductor substrate; doping impurity into the exposed surface area of said semiconductor substrate to form impurity regions serving as source and drain regions; forming a semiconductor layer on the exposed surface of said semiconductor substrate by a growth process; forming a first refractory metal layer on the entire surface of the semiconductor structure; forming an insulation film on said first refractory metal layer; selectively removing said insulation film to form at least one contact hole; forming a second refractory metal layer in said contact hole by a deposition process; removing said insulation film and said first refractory metal layer except that part thereof which lies directly under said second refractory metal layer; and depositing an interlayer insulation film on the entire surface of the semiconductor structure, and planarizing the surface of said interlayer insulation film to expose the surface of said second refractory metal layer.
Claim 3
Independent Claim 30 words
A method for manufacturing MOS semiconductor devices according to clam 1, wherein the step of forming said semiconductor region is effected prior to the step of forming said semiconductor layer.
Claim 4
Independent Claim 30 words
A method for manufacturing MOS semiconductor devices according to clam 1, wherein the step of forming said semiconductor region is effected prior to the step of forming said semiconductor layer.
Claim 5
Dependent Claim 29 words
A method for manufacturing MOS semiconductor devices according to claim 1, wherein the step of forming said semiconductor region is effected after the step of forming said semiconductor layer.
Claim 6
Dependent Claim 32 words
A method for manufacturing MOS semiconductor devices according to claim 1, wherein said first refractory metal layer is formed of a laminated structure of a titanium layer and a titanium nitride layer.
Claim 7
Dependent Claim 23 words
A method for manufacturing MOS semiconductor devices according to claim 1, wherein said second refractory metal layer is formed of a tungsten layer.
Claim 8
Dependent Claim 28 words
A method for manufacturing MOS semiconductor devices according to claim 1, wherein said semiconductor layer is a silicon layer which is formed by a selective epitaxial growth method.

References Cited (Backward Citations)

JPS5688339A Cited
US4378628A Cited
US4488348A Cited
GB2162999A Cited
JPS61183942A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1993-04-09 1993-10-09 1994-04-10 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1997-04-09 1997-10-09 1998-04-10 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2001-04-09 2001-10-09 2002-04-10 $7700.00 Window Closed / Lapsed

Assigned Categories & Tags

No categories assigned to this patent yet.

Assign Category Tag