US4916082A
Expired / Lapsed
US
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Method of preventing dielectric degradation or rupture
Assignee: Motorola Solutions Inc
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Filing: 1989-03-14
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Granted: 1990-04-10
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Expires: 2009-03-14
Abstract
Abstract Charge on a floating gate of a semiconductor device structure is neutralized by illuminating the structure with a high intensity light during process steps that inject charge. The light provides for the formation of electrons, or free carriers, in the semiconductor substrate. The electrons facilitate tunneling which prevents dielectric degradation or rupture.
Inventors
- 👤 Israel A. Lesk
- 👤 Clarence A. Lund
- 👤 Thomas C. Smith
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 00:27
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/60; H10D30/68; H10D30/681; H10D64/00; H10D64/01; H10D64/031; H10D64/035; Y; Y10; Y10S; Y10S438/00; Y10S438/972
Claims Analysis
Total Claims: 15
Claim 1
Independent Claim
92 words
A method of preventing damage to a dielectric layer, comprising the steps of: providing a wafer comprising a semiconductor substrate, the dielectric layer disposed on the substrate, and a floating semiconductor layer disposed on the dielectric layer; subjecting the wafer to a process step that injects charge into the wafer; and illuminating the wafer with light concurrently with the process step that injects charge into the wafer, wherein the light provides for production of electrons in the substrate which facilitates tunneling of the electrons, and thus prevents damage to the dielectric layer.
Claim 2
Independent Claim
92 words
A method of preventing damage to a dielectric layer, comprising the steps of: providing a wafer comprising a semiconductor substrate, the dielectric layer disposed on the substrate, and a floating semiconductor layer disposed on the dielectric layer; subjecting the wafer to a process step that injects charge into the wafer; and illuminating the wafer with light concurrently with the process step that injects charge into the wafer, wherein the light provides for production of electrons in the substrate which facilitates tunneling of the electrons, and thus prevents damage to the dielectric layer.
Claim 3
Dependent Claim
20 words
The method of claim 1 wherein the dielectric layer is a gate dielectric and the floating semiconductor layer is polysilicon.
Claim 4
Dependent Claim
26 words
The method of claim 1 wherein the process step that injects charge is an ion implantation step, a plasma-etching step, or a reactive ion etch step.
Claim 5
Dependent Claim
25 words
The method of claim 1 wherein the light is a high intensity light having a power flux of approximately 2 to 50 mW/cm 2 .
Claim 6
Dependent Claim
23 words
The method of claim 1 wherein the wafer also comprises a masking layer disposed on the dielectric layer and the floating semiconductor layer.
Claim 7
Independent Claim
82 words
A method of preventing damage to a gate dielectric layer, comprising the steps of: providing a wafer comprising a semiconductor substrate, the gate dielectric layer disposed on the substrate, and a floating gate layer disposed on the gate dielectric layer; shining a high intensity light on the wafer concurrently with processing the wafer through a process step which injects charge into the wafer, wherein the light produces electrons in the substrate to facilitate tunneling and prevent rupture of the gate dielectric layer.
Claim 8
Independent Claim
82 words
A method of preventing damage to a gate dielectric layer, comprising the steps of: providing a wafer comprising a semiconductor substrate, the gate dielectric layer disposed on the substrate, and a floating gate layer disposed on the gate dielectric layer; shining a high intensity light on the wafer concurrently with processing the wafer through a process step which injects charge into the wafer, wherein the light produces electrons in the substrate to facilitate tunneling and prevent rupture of the gate dielectric layer.
Claim 9
Dependent Claim
26 words
The method of claim 6 wherein the process step that injects charge is an ion implantation step, a plasmaetching step, or a reactive ion etch step.
Claim 10
Dependent Claim
25 words
The method of claim 6 wherein the light is a high intensity light having a power flux of approximately 2 to 50 mW/cm 2 .
Claim 11
Independent Claim
92 words
A method of preventing damage to a dielectric layer, comprising the steps of: providing a wafer comprising a semiconductor substrate, the dielectric layer disposed on the substrate, and a floating conductor layer disposed on the dielectric layer; subjecting the wafer to a process step that injects charge into the wafer; and illuminating the wafer with light concurrently with the process step that injects charge into the wafer, wherein the light provides for production of electrons in the substrate which facilitates tunneling of the electrons, and thus prevents damage to the dielectric layer.
Claim 12
Independent Claim
92 words
A method of preventing damage to a dielectric layer, comprising the steps of: providing a wafer comprising a semiconductor substrate, the dielectric layer disposed on the substrate, and a floating conductor layer disposed on the dielectric layer; subjecting the wafer to a process step that injects charge into the wafer; and illuminating the wafer with light concurrently with the process step that injects charge into the wafer, wherein the light provides for production of electrons in the substrate which facilitates tunneling of the electrons, and thus prevents damage to the dielectric layer.
Claim 13
Dependent Claim
20 words
The method of claim 9 wherein the dielectric layer is a gate dielectric and the floating conductor layer is metallic.
Claim 14
Dependent Claim
26 words
The method of claim 9 wherein the process step that injects charge is an ion implantation step, a plasmaetching step, or a reactive ion etch step.
Claim 15
Dependent Claim
25 words
The method of claim 9 wherein the light is a high intensity light having a power flux of approximately 2 to 50 mW/cm 2 .
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-04-09 | 1993-10-09 | 1994-04-10 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-04-09 | 1997-10-09 | 1998-04-10 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-04-09 | 2001-10-09 | 2002-04-10 | $7700.00 | Window Closed / Lapsed |