Patent US4914631A successfully refreshed from Google Patents.
US4914631A
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US
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Pull up circuit for sense lines in a semiconductor memory
Assignee: Micron Technology Inc
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Filing: 1988-09-30
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Granted: 1990-04-03
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Expires: 2008-09-30
Abstract
Abstract A memory array (e.g., DRAM) is provided with a potential maintenance circuit which provides sufficient current to maintain a high potential node of the memory array at a predetermined potential. The potential maintenance circuit is gated ON after receipt of a clock signal and gated OFF at the predetermined potential. This permits the high voltage node to be maintained, while reducing current requirements. The invention is particularly useful when used in conjunction with a circuit which rapidly pulls up the high node to a value of V CC -V T (where VT is a threshold voltage of a transistor).
Inventors
- 👤 Gary M. Johnson
- 👤 Zhitong Chen
- 👤 Wen-Foo Chern
- 👤 Ward D. Parkinson
- 👤 Tyler A. Lowrey
- 👤 Thomas M. Trent
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 08:39
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/4063; G11C11/407; G11C11/409; G11C11/4094
Claims Analysis
Total Claims: 18
Claim 1
Independent Claim
278 words
Semiconductor memory device having a memory array, the memory device comprising: (a) a pullup circuit for conducting current from a high potential source to a high potential node of the memory array; (b) a gate control circuit for controlling the current supplied to the high potential node of the memory array from the high potential source, said gate control circuit including a potential maintenance circuit for providing sufficient current from the high potential source to maintain the high potential node of the memory array at a predetermined potential, the potential maintenance circuit being gated ON after receipt of a clock signal and being gated OFF at the predetermined potential; (c) a pair of digit lines coupled to said high potential node and to a low voltage latch node; (d) a first pull down transistor connected between the low voltage latch node and a circuit node, and gated ON in response to a first active signal; (e) a second pull down transistor connected between the circuit node and a low potential source in response to; (f) a voltage control transistor being responsive to a second active signal to conduct current from the low voltage latch node to a gate of the second pull down transistor; (g) a precharge circuit to gate the second pulldown transistor ON prior to the voltage control transistor responding to the second active signal; and (h) a threshold current supply transistor for providing sufficient current from the high potential source to float the low voltage latch node to a predetermined value above a potential of the low voltage source, wherein the threshold voltage supply transistor is gated ON in response to the second active signal.
Claim 2
Dependent Claim
278 words
Semiconductor memory device having a memory array, the memory device comprising: (a) a pullup circuit for conducting current from a high potential source to a high potential node of the memory array; (b) a gate control circuit for controlling the current supplied to the high potential node of the memory array from the high potential source, said gate control circuit including a potential maintenance circuit for providing sufficient current from the high potential source to maintain the high potential node of the memory array at a predetermined potential, the potential maintenance circuit being gated ON after receipt of a clock signal and being gated OFF at the predetermined potential; (c) a pair of digit lines coupled to said high potential node and to a low voltage latch node; (d) a first pull down transistor connected between the low voltage latch node and a circuit node, and gated ON in response to a first active signal; (e) a second pull down transistor connected between the circuit node and a low potential source in response to; (f) a voltage control transistor being responsive to a second active signal to conduct current from the low voltage latch node to a gate of the second pull down transistor; (g) a precharge circuit to gate the second pulldown transistor ON prior to the voltage control transistor responding to the second active signal; and (h) a threshold current supply transistor for providing sufficient current from the high potential source to float the low voltage latch node to a predetermined value above a potential of the low voltage source, wherein the threshold voltage supply transistor is gated ON in response to the second active signal.
Claim 3
Dependent Claim
48 words
Semiconductor memory device as described in claim 1, further comprising: a reference array, and wherein the gate control circuit includes a voltage sensor which senses a potential at a reference node of the reference array and gates OFF the pullup circuit when that potential reaches the predetermined potential.
Claim 4
Dependent Claim
35 words
Semiconductor memory device as described in claim 1, wherein: the gate control circuit provides a signal to gate ON a pullup transistor in said pullup circuit until the high potential node reaches the predetermined potential.
Claim 5
Dependent Claim
29 words
Semiconductor memory device as described in claim 3, wherein: the predetermined potential is the potential of the high potential source reduced by a threshold voltage of the pullup transistor.
Claim 6
Dependent Claim
20 words
Semiconductor memory device as described in claim 1, wherein: the predetermined value is a threshold voltage of an n-channel transistor.
Claim 7
Dependent Claim
47 words
Semiconductor memory device as described in claim 5, further comprising: a reference array, and wherein the gate control circuit includes voltage sensor which senses a potential at a reference node of the reference array and gates OFF the pullup circuit when that potential reaches the predetermined potential.
Claim 8
Dependent Claim
21 words
Semiconductor memory device as described in claim 6, wherein: the semiconductor memory device is a dynamic random access memory (DRAM) device.
Claim 9
Dependent Claim
50 words
Semiconductor memory device as described in claim 1, wherein: the low voltage latch node is coupled to the pair of digit lines through a pair of transistors, the pair of transistors being cross-connected so that each transistor is connected to a terminal, other than the gate, of the other transistor;
Claim 10
Dependent Claim
20 words
Semiconductor memory device as described in claim 8, wherein: the predetermined value is a threshold voltage of an n-channel transistor.
Claim 11
Dependent Claim
40 words
Semiconductor memory device as described in claim 8, wherein: the precharge circuit includes a precharge which provides a precharge potential to gate the second pull down transistor ON prior to the voltage control transistor responding to the second active signal.
Claim 12
Dependent Claim
21 words
Semiconductor memory device as described in claim 8, wherein: the semiconductor memory device is a dynamic random access memory (DRAM) device.
Claim 13
Dependent Claim
31 words
Semiconductor memory device as described in claim 8, wherein: a discharge of said low voltage latch node to ground activates the cross-connected transistors to sense potential differentials between the sense lines.
Claim 14
Dependent Claim
46 words
Semiconductor memory device as described in claim 12, wherein: the second active signal is provided a predetermined time after the first active signal, the predetermined time resulting in a time delay which coincides with a time required for sensing of potential differentials between the sense lines.
Claim 15
Dependent Claim
55 words
Semiconductor memory device as described in claim 13, wherein: the second active signal gates ON the voltage control transistor to thereby supply a signal to the gate of said second pull down transistor which has the same potential as the low voltage latch node, thereby forming a diode configuration of the second pull down transistor.
Claim 16
Dependent Claim
88 words
Semiconductor memory device as described in claim 8, wherein: the threshold current supply transistor is connected to the high potential voltage source through a diode-connected threshold junction device, so that when the threshold current supply transistor is gated ON in response to the second active signal, a leakage path through the threshold current supply transistor and threshold junction device provides a predetermined current to the low voltage latch node to float the low voltage latch node to the predetermined value above the potential of the low voltage source.
Claim 17
Dependent Claim
39 words
Semiconductor memory device as described in claim 15, wherein: a circuit which includes the threshold current supply transistor and said diode connected threshold junction device has a high internal resistance relative to that of the first pull down transistor.
Claim 18
Dependent Claim
21 words
Semiconductor memory device as described in claim 16, wherein: the semiconductor memory device is a dynamic random access memory (DRAM) device.
References Cited (Backward Citations)
US4578778A
Cited
US4679172A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-04-02 | 1993-10-02 | 1994-04-03 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-04-02 | 1997-10-02 | 1998-04-03 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-04-02 | 2001-10-02 | 2002-04-03 | $7700.00 | Window Closed / Lapsed |