US4914439A
Expired / Lapsed
US
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Analog to digital conversion system utilizing dither
Assignee: Teac Corp
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Filing: 1988-09-09
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Granted: 1990-04-03
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Expires: 2008-09-09
Abstract
Abstract A system suitable for digitizing an analog audio signal, with the addition of analog dither to the audio signal and, after the digitization of the resulting analog audio/dither signal, the subtraction of digital dither from the digital audio/dither signal. For the production of the analog and digital dither signals, a digital dither generator is employed which generates digital dither of, e.g., 16 bits. The analog dither signal is derived from this 16 bits dither by first translating the same into analog dither of equivalent magnitude and then by reducing its magnitude to a value equivalent to e.g., 10 bits. The digital dither signal, on the other hand, is provided by reducing the magnitude of the 16 bits digital dither to that of substantially 10 bits. The analog dither signal is added to the audio signal, and the resulting analog audio/dither signal is translated by an analog to digital converter of, e.g., 16 bits into a digital audio/dither signal. Then the substantially 10 bits digital dither signal is subtracted from the digital audio/dither signal. A limiter may be connected to the output of the subtracter for limiting the output level when the analog to digital converter is overloaded.
Inventors
- 👤 Teruyoshi Nakahashi
- 👤 Tetsuji Ono
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 21:42
CPC Classifications
H; H03; H03M; H03M1/00; H03M1/12; H03M1/124; H03M1/129; H03M1/06; H03M1/0617; H03M1/0634; H03M1/0636; H03M1/0639; H03M1/0641
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
286 words
An analog to digital conversion system comprising: (a) input means for inputting an analog information signal (A1) to be digitized; (b) a digital dither generator for generating a first digital dither signal of m bits; (c) a digital to analog converter connected to the digital dither generator for translating the first digitial signal of m bits into a first analog dither signal of equivalent magnitude; (d) analog level reduction means connected to the digital to analog converter for reducing the magnitude of the first analog dither signal and providing a second analog dither signal (B1) equivalent in magnitude to a digital dither signal of 1 bits, where 1 is less than m; (e) an adder connected to both the input means and the analog level reduction means for adding the second analog dither signal (B1) to the analog information signal (A1) and providing an analog information/dither signal (A1+B1); (f) an analog to digital converter connected to the adder for translating the analog information/dither signal (A1+B1) into a digital information/dither signal (A2+B2) of n bits, where n is equal, or not equal, to m and greater than 1; (g) a digital level reduction circuit connected to the digital dither generator for translating the first digital dither signal of m bits into a second digital dither signal (B2) of substantially 1 bits, the 1 bits of the second digital dither signal being composed of the 1 consecutive bits, including the most significant bit, of the first digital dither signal; and (h) a subtracter connected to both the analog to digital converter and the digital level reduction circuit for subtracting the second digital dither signal (B2) from the digital information/dither signal (A2+B2) and providing a digital information signal (A2).
Claim 2
Dependent Claim
286 words
An analog to digital conversion system comprising: (a) input means for inputting an analog information signal (A1) to be digitized; (b) a digital dither generator for generating a first digital dither signal of m bits; (c) a digital to analog converter connected to the digital dither generator for translating the first digitial signal of m bits into a first analog dither signal of equivalent magnitude; (d) analog level reduction means connected to the digital to analog converter for reducing the magnitude of the first analog dither signal and providing a second analog dither signal (B1) equivalent in magnitude to a digital dither signal of 1 bits, where 1 is less than m; (e) an adder connected to both the input means and the analog level reduction means for adding the second analog dither signal (B1) to the analog information signal (A1) and providing an analog information/dither signal (A1+B1); (f) an analog to digital converter connected to the adder for translating the analog information/dither signal (A1+B1) into a digital information/dither signal (A2+B2) of n bits, where n is equal, or not equal, to m and greater than 1; (g) a digital level reduction circuit connected to the digital dither generator for translating the first digital dither signal of m bits into a second digital dither signal (B2) of substantially 1 bits, the 1 bits of the second digital dither signal being composed of the 1 consecutive bits, including the most significant bit, of the first digital dither signal; and (h) a subtracter connected to both the analog to digital converter and the digital level reduction circuit for subtracting the second digital dither signal (B2) from the digital information/dither signal (A2+B2) and providing a digital information signal (A2).
Claim 3
Dependent Claim
19 words
The analog to digital conversion system of claim 1 wherein the analog level reduction means comprises a variable resistor.
Claim 4
Dependent Claim
29 words
The analog to digital conversion system of claim 1 wherein the second analog dither signal (B1) fed to the adder is of one or other of two opposite polarities.
Claim 5
Dependent Claim
76 words
The analog to digital conversion system of claim 1 further comprising: (a) an overload detector circuit connected to the subtracter for detecting the overloading of the analog to digital converter by the input analog information/dither signal (A1+B1); and (b) a limiter connected to both the subtracter and the overload detector circuit for limiting the magnitude of the digital information signal (A2) while the analog to digital converter is being overloaded by the analog information/dither signal (A1+B1).
Claim 6
Dependent Claim
87 words
The analog to digital conversion system of claim 4 wherein the analog to digital converter and the subtracter produces the outputs in the form of two's complement, and wherein the overload detector circuit comprises: (a) a positive overload detector circuit responsive to the two's complement output from the subtracter for detecting the positive overloading of the analog to digital converter; and (b) a negative overload detector circuit responsive to the two's complement output from the subtracter for detecting the negative overloading of the analog to digital converter.
Claim 7
Dependent Claim
153 words
The analog to digital conversion system of claim 4 wherein the analog to digital converter has a positive overload level (+L) and a negative overload level (-L) of the same absolute value, wherein the second analog dither signal (B1) is of negative polarity, and wherein the overload detector circuit comprises: (a) a positive overload detector circuit for detecting whether or not the magnitude of the digital information signal (A2) is up to a positive detection level (L1), the positive detection level (L1) being equal to the positive overload level (+L) of the analog to digital converter; and (b) a negative overload detector circuit for detecting whether or not the magnitude of the digital information signal (A2) is up to a negative detection level (L2), the negative detection level (L2) being higher than the negative overload level (-L) of the analog to digital converter approximately by the magnitude of the second dither signal (B1).
Claim 8
Dependent Claim
153 words
The analog to digital conversion system of claim 4 wherein the analog to digital converter has a positive overload level (+L) and a negative overload level (-L) of the same absolute value, wherein the second analog dither signal B1 is of positive polarity, and wherein the overload detector circuit comprises: (a) a positive overload detector circuit for detecting whether or not the magnitude of the digital information signal (A2) is up to a positive detection level (L1), the positive detection level (L1) being lower than the positive overload level (+L) of the analog to digital converter approximately by the magnitude of the digital dither signal (B1); and (b) a negative overload detector circuit for detecting whether or not the magnitude of the digital information signal (A2) is up to a negative detection level (L2), the negative detection level (L1) being equal to the negative overload level (-L) of the analog to digital converter.
Claim 9
Dependent Claim
32 words
The analog to digital conversion system of claim 4 further comprising a warning device connected to the overload detector circuit for giving a warning when the analog to digital converter is overloaded.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-04-02 | 1993-10-02 | 1994-04-03 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-04-02 | 1997-10-02 | 1998-04-03 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-04-02 | 2001-10-02 | 2002-04-03 | $7700.00 | Window Closed / Lapsed |