US4812846A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Dither circuit using dither including signal component having frequency half of sampling frequency
Assignee: Yamaha Corp
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Filing: 1988-07-19
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Granted: 1989-03-14
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Expires: 2008-07-19
Abstract
Abstract A dither circuit for improving linearity in A/D or D/A conversion by adding dither to an input signal of an A/D or D/A converter and subtracting dither from an output signal of the A/D or D/A converter. The dither circuit comprises a 1/2 Fs signal generator for generating a 1/2 Fs signal having a frequency which is 1/2 of a sampling frequency Fs, a noise generator for generating random noise in digital form and an adder for adding the 1/2 Fs signal and the random noise together and supplying a resulting sum signal to the adder and subtractor as dither. According to this invention, a conversion error is reduced with a result that the random noise can be of a small level. Thus, high accuracy requirement in a practical circuit construction is reduced so that the circuit construction is easily performed.
Inventors
- 👤 Masao Noro
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 15:00
CPC Classifications
H; H04; H04B; H04B14/00; H04B14/02; H04B14/04; H04B14/046; H03; H03M; H03M1/00; H03M1/06; H03M1/0617; H03M1/0634; H03M1/0636; H03M1/0639
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
131 words
A dither circuit comprising: an A/D converter; an adder provided in a prior stage to said A/D converter; a subtractor provided in a posterior stage to said A/D converter; and dither supplying means for supplying dither to said adder and subtractor, said dither supplying means comprising: a 1/2 Fs signal generator for generating a 1/2 Fs signal having a frequency which is 1/2 of a sampling frequency Fs to provide a first dither component; a noise generator for generating random noise to provide a second dither component; and an adder for adding the 1/2 Fs signals and the random noise together and supplying a resulting sum signal to said adder and subtractor as dither, said dither including said first and second dither components to increase conversion linearity and reduce quantizing noise.
Claim 2
Dependent Claim
131 words
A dither circuit comprising: an A/D converter; an adder provided in a prior stage to said A/D converter; a subtractor provided in a posterior stage to said A/D converter; and dither supplying means for supplying dither to said adder and subtractor, said dither supplying means comprising: a 1/2 Fs signal generator for generating a 1/2 Fs signal having a frequency which is 1/2 of a sampling frequency Fs to provide a first dither component; a noise generator for generating random noise to provide a second dither component; and an adder for adding the 1/2 Fs signals and the random noise together and supplying a resulting sum signal to said adder and subtractor as dither, said dither including said first and second dither components to increase conversion linearity and reduce quantizing noise.
Claim 3
Dependent Claim
45 words
A dither circuit as defined in claim 1 wherein said dither supplying means further comprises a D/A converter connected to said adder provided in a prior stage to said A/D converter for converting the dither supplied from said dither supplying means to an analog signal.
Claim 4
Dependent Claim
36 words
A dither circuit as defined in claim 1 wherein said dither supplying means further comprises a D/A converter connected to said subtractor for converting the dither supplied from said dither supplying means to an analog signal.
Claim 5
Dependent Claim
131 words
A dither circuit comprising: a D/A converter; an adder provided in a prior stage to said D/A converter; a subtractor provided in a posterior stage to said D/A converter; and dither supplying means for supplying dither to said adder and subtractor, said dither supplying means comprising: a 1/2 Fs signal generator for generating a 1/2 Fs signal having a frequency which is 1/2 of a sampling frequency Fs to provide a first dither component; a noise generator for generating random noise to provide a second dither component; and an adder for adding the 1/2 Fs signal and the random noise together and supplying a resulting sum signal to said adder and subtractor as dither, said dither including said first and second dither components to increase conversion linearity and reduce quantizing noise.
Claim 6
Dependent Claim
131 words
A dither circuit comprising: a D/A converter; an adder provided in a prior stage to said D/A converter; a subtractor provided in a posterior stage to said D/A converter; and dither supplying means for supplying dither to said adder and subtractor, said dither supplying means comprising: a 1/2 Fs signal generator for generating a 1/2 Fs signal having a frequency which is 1/2 of a sampling frequency Fs to provide a first dither component; a noise generator for generating random noise to provide a second dither component; and an adder for adding the 1/2 Fs signal and the random noise together and supplying a resulting sum signal to said adder and subtractor as dither, said dither including said first and second dither components to increase conversion linearity and reduce quantizing noise.
Claim 7
Dependent Claim
122 words
An analog-to-digital conversion circuit including subtractive-type dither comprising: an analog-to-digital converter; dither supplying means for supplying dither, said dither supplying means including (a) a 1/2 Fs generator for generating a first dither component comprised of a periodic signal of relatively large amplitude and a frequency which is 1/2 of sampling frequency of said analog-to-digital converter, and (b) a noise generator for generating a second dither component comprised of a noise signal of relatively small amplitude; an adder for adding the dither to an analog input signal, wherein the output of the adder is provided to the analog-to-digital converter; and a subtractor for subtracting the dither from the output of the analog-to-digital converter, said circuit providing improved conversion accuracy and reduced quantization noise.
Claim 8
Dependent Claim
122 words
An analog-to-digital conversion circuit including subtractive-type dither comprising: an analog-to-digital converter; dither supplying means for supplying dither, said dither supplying means including (a) a 1/2 Fs generator for generating a first dither component comprised of a periodic signal of relatively large amplitude and a frequency which is 1/2 of sampling frequency of said analog-to-digital converter, and (b) a noise generator for generating a second dither component comprised of a noise signal of relatively small amplitude; an adder for adding the dither to an analog input signal, wherein the output of the adder is provided to the analog-to-digital converter; and a subtractor for subtracting the dither from the output of the analog-to-digital converter, said circuit providing improved conversion accuracy and reduced quantization noise.
Claim 9
Dependent Claim
123 words
An digital-to-analog conversion circuit including subtractive-type dither comprising: a digital-to-analog converter; dither supplying means for supplying dither, said dither supplying means including (a) a 1/2 Fs generator for generating a first dither component comprised of a periodic signal of relatively large amplitude and a frequency which is 1/2 of a sampling frequency of said digital-to-analog converter, and (b) a noise generator for generating a second dither component comprised of a noise signal of relatively small amplitude; an adder for adding the dither to an digital input signal, wherein the output of the adder is provided to the digital-to-analog converter; and a subtractor for subtracting the dither from the output of the digital-to-analog converter, said circuit providing improved conversion accuracy and reduced quantization noise.
Claim 10
Dependent Claim
123 words
An digital-to-analog conversion circuit including subtractive-type dither comprising: a digital-to-analog converter; dither supplying means for supplying dither, said dither supplying means including (a) a 1/2 Fs generator for generating a first dither component comprised of a periodic signal of relatively large amplitude and a frequency which is 1/2 of a sampling frequency of said digital-to-analog converter, and (b) a noise generator for generating a second dither component comprised of a noise signal of relatively small amplitude; an adder for adding the dither to an digital input signal, wherein the output of the adder is provided to the digital-to-analog converter; and a subtractor for subtracting the dither from the output of the digital-to-analog converter, said circuit providing improved conversion accuracy and reduced quantization noise.
References Cited (Backward Citations)
US3877022A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-03-13 | 1992-09-12 | 1993-03-14 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-03-13 | 1996-09-12 | 1997-03-14 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-03-13 | 2000-09-12 | 2001-03-14 | $7700.00 | Window Closed / Lapsed |