Patent US4912710A successfully refreshed from Google Patents.
US4912710A
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Self-checking random access memory
Assignee: Harris Corp
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Filing: 1988-02-29
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Granted: 1990-03-27
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Expires: 2008-02-29
Abstract
Abstract A random access memory including address error checking. The random access memory includes an address decoder that activates data cells from among the plurality of data cells in the memory. The random access memory also includes an address encoder that supplies an address determined by the data cells activated. The address from the encoder is compared with the address input to the decoder and if the two address are different an error indication is provided.
Inventors
- 👤 Robert M. Rolfe
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 03:44
CPC Classifications
G; G11; G11C; G11C29/00; G11C29/02; G11C29/024
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
150 words
A random access memory having memory locations for storing data words, wherein each data word has N data bits and is uniquely addressable, and wherein a data bit is stored in each memory location, said random access memory comprising: means for providing a requested address: means for decoding said requested address to identify the requested memory locations corresponding to said requested address and for activating memory locations in response thereto, wherein due to circuit faults the activated memory locations may differ from the requested memory locations; a data bus; means for transferring data between said activated memory locations and said data bus; encoder means responsive to said activated memory locations to provide an activated address identifying the location of said activated memory locations; fault detector means for comparing said requested address and said activated address and for indicating an error when said requested address is different from said activated address.
Claim 2
Dependent Claim
150 words
A random access memory having memory locations for storing data words, wherein each data word has N data bits and is uniquely addressable, and wherein a data bit is stored in each memory location, said random access memory comprising: means for providing a requested address: means for decoding said requested address to identify the requested memory locations corresponding to said requested address and for activating memory locations in response thereto, wherein due to circuit faults the activated memory locations may differ from the requested memory locations; a data bus; means for transferring data between said activated memory locations and said data bus; encoder means responsive to said activated memory locations to provide an activated address identifying the location of said activated memory locations; fault detector means for comparing said requested address and said activated address and for indicating an error when said requested address is different from said activated address.
Claim 3
Dependent Claim
25 words
The random access memory of claim 1 wherein the encoder means provides a plurality of activated addresses equal to the number of data words activated.
Claim 4
Independent Claim
95 words
A method of accessing a random access memory, including the steps of: providing a requested address; decoding said requested address to identify the requested memory locations corresponding to said requested address and to activate memory locations in response thereto, wherein due to circuits faults the activated memory location may differ from the requested memory locations; transferring data between said activated memory locations and a data bus; determining the address of said activated memory locations; comparing said requested address and said activated address; indicating an error when said requested address is different from said activated address.
Claim 5
Independent Claim
95 words
A method of accessing a random access memory, including the steps of: providing a requested address; decoding said requested address to identify the requested memory locations corresponding to said requested address and to activate memory locations in response thereto, wherein due to circuits faults the activated memory location may differ from the requested memory locations; transferring data between said activated memory locations and a data bus; determining the address of said activated memory locations; comparing said requested address and said activated address; indicating an error when said requested address is different from said activated address.
Claim 6
Dependent Claim
20 words
The method of claim 3 wherein the number of activated addresses is equal to the number of activated data words.
Claim 7
Dependent Claim
147 words
An error detector circuit for testing a random access memory having uniquely addressable memory locations for storing data bits, and wherein a data bit is stored in each memory location, said error detector circuit comprising: means for providing a requested address; means for decoding said requested address to identify the requested memory locations corresponding to said requested address and for activating the requested memory locations in response thereto wherein due to circuits faults the activated memory locations may differ from the requested memory locations; a data bus; means for transferring data between said activated memory locations and said data bus; encoder means responsive to said activated memory locations to provide an activated address identifying the location of said activated memory locations; detector means for comparing said requested address and said activated address and for indicating an error when said requested address is different from said activated address.
Claim 8
Dependent Claim
147 words
An error detector circuit for testing a random access memory having uniquely addressable memory locations for storing data bits, and wherein a data bit is stored in each memory location, said error detector circuit comprising: means for providing a requested address; means for decoding said requested address to identify the requested memory locations corresponding to said requested address and for activating the requested memory locations in response thereto wherein due to circuits faults the activated memory locations may differ from the requested memory locations; a data bus; means for transferring data between said activated memory locations and said data bus; encoder means responsive to said activated memory locations to provide an activated address identifying the location of said activated memory locations; detector means for comparing said requested address and said activated address and for indicating an error when said requested address is different from said activated address.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-03-26 | 1993-09-25 | 1994-03-27 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-03-26 | 1997-09-25 | 1998-03-27 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-03-26 | 2001-09-25 | 2002-03-27 | $7700.00 | Window Closed / Lapsed |