Image memory having plural input registers and output registers to provide random and serial accesses

Claim 2

An image memory comprising: a plurality of memory devices; a plurality of registers for writing each connected to a data input portion of each of said memory devices; a plurality of registers for reading each connected to a data output portion of each of said memory devices; a random access bus connected to said registers for writing and registers for reading; a serial access bus connected to said registers for writing and said registers for reading; and a control circuit controlling said memory devices, said registers for writing and said registers for reading, thereby freely selecting, random write control in which data inputted from said random access bus to said registers for writing is written only in a memory device selected from said memory devices, random read control in which data of said memory devices are inputted to said registers for reading and only a selected data is outputted to said random access bus, serial write control in which serial data from said serial access bus are held in said registers for writing as parallel data and are simultaneously written in respective said memory devices, and serial read control in which parallel data simultaneously read from said respective memory devices are held in said registers for reading and serially outputted to said serial access bus.

Claim 3

An image memory according to claim 1, wherein said register for writing and said register for reading are formed of transparent type latches.

Claim 4

An image memory according to claim 1, wherein said control circuit is adapted for simultaneously selecting said serial write control and said serial read control.

Claim 5

An image memory comprising: a plurality of registers for writing each connected to a data input portion of each of said memory devices; a plurality of first registers for reading each connected to a data output portion of each of said memory devices; a plurality of second registers for reading each connected to a data output portion of each of said memory devices; a random access bus connected to said registers for writing and said first and second registers for reading; a serial access bus connected to said registers for writing and said first registers for reading; and a control circuit controlling said memory devices, said registers for writing and said first and second registers for reading, thereby freely selecting random write control in which said memory devices, said registers for writing and said first and second registers for reading are controlled and whereby data inputted from said random access bus to said registers for writing are written only in a memory device selected from said memory devices, random read control in which data from said memory devices are inputted to at least one of said first and second registers for reading and only a selected data is outputted to said random access bus, serial write control in which serial data from said serial access bus are held as parallel data in said registers for writing and simultaneously written in respective said memory devices, serial read control in which parallel data simultaneously read from said respective memory devices are held in said first registers for reading and serially outputted to the serial access bus, first mixed control in which said serial read control is mixed with said random write control, and second mixed control in which said serial read control is mixed with random read control in which data from said memory devices are inputted to said second registers for reading and only a selected data is outputted to said random access bus.

Claim 6

An image memory comprising: a plurality of registers for writing each connected to a data input portion of each of said memory devices; a plurality of first registers for reading each connected to a data output portion of each of said memory devices; a plurality of second registers for reading each connected to a data output portion of each of said memory devices; a random access bus connected to said registers for writing and said first and second registers for reading; a serial access bus connected to said registers for writing and said first registers for reading; and a control circuit controlling said memory devices, said registers for writing and said first and second registers for reading, thereby freely selecting random write control in which said memory devices, said registers for writing and said first and second registers for reading are controlled and whereby data inputted from said random access bus to said registers for writing are written only in a memory device selected from said memory devices, random read control in which data from said memory devices are inputted to at least one of said first and second registers for reading and only a selected data is outputted to said random access bus, serial write control in which serial data from said serial access bus are held as parallel data in said registers for writing and simultaneously written in respective said memory devices, serial read control in which parallel data simultaneously read from said respective memory devices are held in said first registers for reading and serially outputted to the serial access bus, first mixed control in which said serial read control is mixed with said random write control, and second mixed control in which said serial read control is mixed with random read control in which data from said memory devices are inputted to said second registers for reading and only a selected data is outputted to said random access bus.

Claim 7

An image memory according to claim 4, wherein said register for writing and said first register for reading are formed of transparent type latches.

Claim 8

An image memory according to claim 4, wherein said control circuit is adapted for simultaneously selecting said serial write control and serial read control.