US4802133A
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US
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Logic circuit
Assignee: Toshiba Corp
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Filing: 1986-03-26
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Granted: 1989-01-31
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Expires: 2006-03-26
Abstract
Abstract A logic circuit which can easily perform a logical function test is disclosed. A first type of the logic circuit comprises a combinational circuit having a plurality of internal nodes, node data latch circuits respectively connected to the preselected internal nodes for latching their logical states, and readout means for reading data latched in the latch circuits by using a data transfer clock. Further, there may be adopted implementation such that the node data latch circuit functions to allow a predetermined node to be placed in the logical state latched in the node data latch circuit. Thus, this first type of the logic circuit makes it possible to monitor even logical states of internal nodes of the combinational circuit. A second type of the logic circuit comprises a combinational circuits, a plurality of memory means, designation means e.g. a flip-flops provided per each memory means for designating whether an access to the memory means is enabled or not, access means for providing an access to the memory means designated by the designation means, and means for setting designation data to the designation means. Further, there may be provided an address decoder for decoding addresses assigned to the respective designation means. Thus, the second type of the logic circuit can implement a logical function test with less additional circuitry and wiring and in a simplified control mode. In addition, the combination of the first and second types of the logic circuits is also possible.
Inventors
- 👤 Akira Kanuma
- 👤 Toshiyuki Yaguchi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 10:54
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/3181; G01R31/3185; G01R31/318533; G01R31/318558; G01R31/318572
Claims Analysis
Total Claims: 21
Claim 1
Independent Claim
120 words
A logic circuit comprising: a combinational circuit having a plurality of internal nodes; a plurality of latch circuits respectively connected to preselected internal nodes of said plurality of internal nodes for latching logical states thereof; and readout means for reading data latched in said respective latch circuits, wherein said readout means comprises: a bus line for transmitting said data read from said latch circuit, an address decoder for decoding addresses indicative of a location of said latch circuits, and gates interconnected between said latch circuits and said bus line for effecting a switching operation in response to signals decoded from said address decoder, wherein said readout means reads data in the latch circuit and transfers same to said bus line.
Claim 2
Dependent Claim
120 words
A logic circuit comprising: a combinational circuit having a plurality of internal nodes; a plurality of latch circuits respectively connected to preselected internal nodes of said plurality of internal nodes for latching logical states thereof; and readout means for reading data latched in said respective latch circuits, wherein said readout means comprises: a bus line for transmitting said data read from said latch circuit, an address decoder for decoding addresses indicative of a location of said latch circuits, and gates interconnected between said latch circuits and said bus line for effecting a switching operation in response to signals decoded from said address decoder, wherein said readout means reads data in the latch circuit and transfers same to said bus line.
Claim 3
Dependent Claim
38 words
A logic circuit according to claim 1, wherein said latch circuits are connected in series, said readout means sequentially transferring data latched in said latch circuits in synchronism with a data transfer clock to read the data transferred.
Claim 4
Dependent Claim
96 words
A logic circuit comprising: a combinational circuit having a plurality of internal nodes; a plurality of memory means respectively connected to selected internal nodes of said plurality internal nodes; means for allowing said memory means to latch logical states of said preselected internal nodes and for allowing said memory means to output logical states latched in said memory means to said preselected internal nodes; and an address decoder for decoding addresses specifying ones of said memory means, data being inputted into the memory means selected by signals decoded by said address decoder or being outputted therefrom.
Claim 5
Dependent Claim
96 words
A logic circuit comprising: a combinational circuit having a plurality of internal nodes; a plurality of memory means respectively connected to selected internal nodes of said plurality internal nodes; means for allowing said memory means to latch logical states of said preselected internal nodes and for allowing said memory means to output logical states latched in said memory means to said preselected internal nodes; and an address decoder for decoding addresses specifying ones of said memory means, data being inputted into the memory means selected by signals decoded by said address decoder or being outputted therefrom.
Claim 6
Dependent Claim
34 words
A logic circuit according to claim 3, wherein said plurality of memory means are connected in series to serially input data to said plurality of memory means connected in series or output data therefrom.
Claim 7
Dependent Claim
100 words
A logic circuit comprising: a combinational circuit; a plurality of memory means connected to said combinational circuit; designation means provided per each of said plurality of memory means for designating whether an access to said memory means is enabled or not; access means for reading data from the memory means designated by said designated means or writing data thereinto; and means for setting designation data to said designation means, wherein said setting means has means for decoding addresses of said plurality of designation means, designation data being set to designation means assigned to an address decoded by said decoding means.
Claim 8
Dependent Claim
100 words
A logic circuit comprising: a combinational circuit; a plurality of memory means connected to said combinational circuit; designation means provided per each of said plurality of memory means for designating whether an access to said memory means is enabled or not; access means for reading data from the memory means designated by said designated means or writing data thereinto; and means for setting designation data to said designation means, wherein said setting means has means for decoding addresses of said plurality of designation means, designation data being set to designation means assigned to an address decoded by said decoding means.
Claim 9
Dependent Claim
37 words
A logic circuit according to claim 5, wherein said plurality of designation means are connected in series, and wherein said setting means serially inputs designation data in sequence to said plurality of designation means connected in series.
Claim 10
Dependent Claim
33 words
A logic circuit according to claim 5, wherein said plurality of designation means are connected in a ring-shaped manner, said setting means serially transferring designation data set in said plurality of designation means.
Claim 11
Dependent Claim
181 words
A logic circuit comprising: a combinational circuit having a plurality of internal nodes; a plurality of memory means connected to said combinational circuit; designation means provided per each of said plurality of memory means for designating whether an access to said memory means is enabled or not; accesss means for reading data from the memory means designated by said designation means or writing data thereinto; means for setting designation data to said designation means; latch means respectively connected to preselected internal nodes of said plurality of internal nodes for latching logical states of said preselected internal nodes; and readout means for reading the data latched in said latch means, wherein said readout means comprises a bus line for reading said data in said latch means, an address decoder for decoding addresses indicative of the location of said latch circuits, and gates interconnected between said latch ciruits and said bus line for effecting a switching operation in response to signals decoded from said address decoder, wherein said readout means reads data in the latch means and transfers same to said bus line.
Claim 12
Dependent Claim
181 words
A logic circuit comprising: a combinational circuit having a plurality of internal nodes; a plurality of memory means connected to said combinational circuit; designation means provided per each of said plurality of memory means for designating whether an access to said memory means is enabled or not; accesss means for reading data from the memory means designated by said designation means or writing data thereinto; means for setting designation data to said designation means; latch means respectively connected to preselected internal nodes of said plurality of internal nodes for latching logical states of said preselected internal nodes; and readout means for reading the data latched in said latch means, wherein said readout means comprises a bus line for reading said data in said latch means, an address decoder for decoding addresses indicative of the location of said latch circuits, and gates interconnected between said latch ciruits and said bus line for effecting a switching operation in response to signals decoded from said address decoder, wherein said readout means reads data in the latch means and transfers same to said bus line.
Claim 13
Dependent Claim
38 words
A logic circuit according to claim 8, wherein said latch means are connected in series, said readout means sequentially transferring data latched in said latch means in synchronism with a data transfer clock to read the data transferred.
Claim 14
Dependent Claim
35 words
A logic circuit according to claim 8, wherein said plurality of designation means are connected in series, said setting means serially inputting designated data in sequence to said plurality of designation means connected in series.
Claim 15
Dependent Claim
33 words
A logic circuit according to claim 8, wherein said plurality of designation means are connected in a ring-shaped manner, said setting means sequentially transferring designation data set in said plurality of designation means.
Claim 16
Dependent Claim
38 words
A logic circuit according to claim 8, wherein said setting means has means for decoding addresses of said plurality of designation means, designation data being set to designation means assigned to an address decoded by said decoding means.
Claim 17
Dependent Claim
140 words
A logic circuit comprising: a combinational circuit having a plurality of internal nodes; a plurality of latch circuits respectively connected to preselected internal nodes of said plurality of internal nodes for latching logical states thereof, said plurality of latching circuits only connected for receiving data from said combinational circuit and not for supplying data thereto; and readout means for reading data latched in said respective latch circuits, wherein said readout means comprises: a bus line for transmitting said data read from said latch circuit; an address decoder for decoding addresses indicative of a location of said latch circuits; and gates interconnected between said latch circuits and said bus line for effecting a switching operation in response to signals decoded from said address decoder; wherein said readout means reads data in the latch circuit and transfers same to said bus line.
Claim 18
Dependent Claim
140 words
A logic circuit comprising: a combinational circuit having a plurality of internal nodes; a plurality of latch circuits respectively connected to preselected internal nodes of said plurality of internal nodes for latching logical states thereof, said plurality of latching circuits only connected for receiving data from said combinational circuit and not for supplying data thereto; and readout means for reading data latched in said respective latch circuits, wherein said readout means comprises: a bus line for transmitting said data read from said latch circuit; an address decoder for decoding addresses indicative of a location of said latch circuits; and gates interconnected between said latch circuits and said bus line for effecting a switching operation in response to signals decoded from said address decoder; wherein said readout means reads data in the latch circuit and transfers same to said bus line.
Claim 19
Dependent Claim
38 words
A logic circuit according to claim 13, wherein said latch circuits are connected in series, said readout means sequentially transferring data latched in said latch circuits in synchronism with a data transfer clock to read the data transferred.
Claim 20
Dependent Claim
140 words
A logic circuit comprising: a combinational circuit having a plurality of internal nodes; a plurality of memory means connected to said combinational circuit; designation means provided per each of said plurality of memory means for designating whether an access to said memory means is enabled or not; access means for reading data from the memory means designated by said designation means or writing data thereinto; means for setting designation data to said designation means; latch means respectively connected to preselected internal nodes of said plurality of internal nodes for latching logical states of said preselected internal nodes; and readout means for reading the data latched in said latch means; wherein said setting means has means for decoding addresses of said plurality of designation means, designation data being set to designation means assigned to an address decoded by said decoding means.
Claim 21
Dependent Claim
140 words
A logic circuit comprising: a combinational circuit having a plurality of internal nodes; a plurality of memory means connected to said combinational circuit; designation means provided per each of said plurality of memory means for designating whether an access to said memory means is enabled or not; access means for reading data from the memory means designated by said designation means or writing data thereinto; means for setting designation data to said designation means; latch means respectively connected to preselected internal nodes of said plurality of internal nodes for latching logical states of said preselected internal nodes; and readout means for reading the data latched in said latch means; wherein said setting means has means for decoding addresses of said plurality of designation means, designation data being set to designation means assigned to an address decoded by said decoding means.
References Cited (Backward Citations)
US3961254A
Cited
DE2826722A1
Cited
US4140967A
Cited
US4212026A
Cited
US4424581A
Cited
US4669061A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-01-31 | 1992-08-01 | 1993-01-31 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-01-31 | 1996-08-01 | 1997-01-31 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-01-31 | 2000-08-01 | 2001-01-31 | $7700.00 | Window Closed / Lapsed |