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US4908745A
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Sequence controller
Assignee: Hitachi Ltd
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Filing: 1987-10-07
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Granted: 1990-03-13
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Expires: 2007-10-07
Abstract
Abstract In cyclically executing the sequence, a signal that informs the controller of the occurrence of a interrupt factor is input to an external signal input terminal. When there are many interrupt factors, it is necessary to quickly analyze the interrupt factors. In this invention, the external signal input terminal is divided into a plurality of blocks, and at least one block is further divided into a plurality of groups. When there develops even one interrupt factor, the data thereof is readily transmitted to a basic unit, and the block in which the interrupt factor has developed raises a flag to inform the controller of this fact. Upon receipt of the above data, the basic unit successively looks for the flags in the blocks. When a flag is detected, the basic unit then successively examines a group that has issued a signal that informs the controller of the occurrence of the interrupt factor in the block in which the flag was found.
Inventors
- 👤 Yoji Ichiyasu
- 👤 Katuhiro Fujiwara
- 👤 Oshiga Takayasu
- 👤 Toshiro Kasahara
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 06:04
CPC Classifications
G; G05; G05B; G05B19/00; G05B19/02; G05B19/04; G05B19/042; G05B19/0423
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
267 words
A sequence controller comprising: a program storage means for storing a sequence program; external signal input terminals divided into multiple blocks, at least one block being subdivided into multiple groups, each group consisting of multiple terminals; an arithmetic and logic operation means having a timing signal generating circuit for producing a timing signal, the arithmetic and logic operation means being adapted to perform logic operation on two or more signals including the external signals taken in from the external signal input terminals, according to a sequence program read out from the program storage means in synchronism with the timing signal; an output means for outputting a control signal according to the result of operation performed by the arithmetic and logic operation means; first signal generating means for outputting a first signal when a signal calling for an interrupt processing comes to a group of the external signal input terminals; second signal generating means for outputting a second signal when one of the blocks outputs the first signal; a second signal transfer means for informing the arithmetic and logic operation means that the second signal has occurred in one of the blocks; and an access means by which the arithmetic and logic operation means when informed by the second signal transfer means of the occurrence of the second signal stops its logic operation required by the sequence program, accesses the second signal generating means successively and, when it finds the block that has produced the second signal, successively accesses the first signal generating means belonging to that block to identify the unit which has outputted the first signal.
Claim 2
Dependent Claim
267 words
A sequence controller comprising: a program storage means for storing a sequence program; external signal input terminals divided into multiple blocks, at least one block being subdivided into multiple groups, each group consisting of multiple terminals; an arithmetic and logic operation means having a timing signal generating circuit for producing a timing signal, the arithmetic and logic operation means being adapted to perform logic operation on two or more signals including the external signals taken in from the external signal input terminals, according to a sequence program read out from the program storage means in synchronism with the timing signal; an output means for outputting a control signal according to the result of operation performed by the arithmetic and logic operation means; first signal generating means for outputting a first signal when a signal calling for an interrupt processing comes to a group of the external signal input terminals; second signal generating means for outputting a second signal when one of the blocks outputs the first signal; a second signal transfer means for informing the arithmetic and logic operation means that the second signal has occurred in one of the blocks; and an access means by which the arithmetic and logic operation means when informed by the second signal transfer means of the occurrence of the second signal stops its logic operation required by the sequence program, accesses the second signal generating means successively and, when it finds the block that has produced the second signal, successively accesses the first signal generating means belonging to that block to identify the unit which has outputted the first signal.
Claim 3
Dependent Claim
78 words
A sequence controller as set forth in claim 1, wherein the timing signal generating circuit is a program counter which outputs a memory address signal in synchronism with the timing signal and the arithmetic and logic operation means performs logic operations on two or more signals including the external signals taken in from the external signal input terminals, according to the sequence program which was read out from the program storage means according to the memory address signal.
Claim 4
Dependent Claim
32 words
A sequence controller as set forth in claim 1, wherein the first signal generating means outputs the first signal when a signal enters a particular one of the external signal input terminals.
Claim 5
Dependent Claim
298 words
A sequence controller comprising: a program storage means for storing a sequence program; external signal input terminals divided into multiple blocks, at least one block being subdivided into multiple groups, each group consisting of multiple terminals; an arithmetic and logic operation means having a program counter for outputting a memory address signal in synchronism with a timing signal, the arithmetic and logic operation means being adapted to perform logic operation on two or more signals including the external signals taken in from the external signal input terminals, according to a sequence program which was read out from the program storage means according to the memory address signal; an output means for outputting a control signal according to the result of operation performed by the arithmetic and logic operation means; a specifying means for specifying some of the external signal input terminals as an interrupt signal input terminal; first signal generating means for outputting a first signal when a signal calling for an interrupt processing comes to a particular terminal in a group to which the interrupt signal input terminals belong; second signal generating means for outputting a second signal when one of the blocks outputs the first signal; a second signal transfer means for informing the arithmetic and logic operation means that the second signal has occurred in one of the blocks; and an access means by which the arithmetic and logic operation means when informed by the second signal transfer means of the occurrence of the second signal stops its logic operation required by the sequence program, accesses the second signal generating means successively and, when it finds the block that has produced the second signal, successively accesses the first signal generating means belonging to that block to identify the unit which has outputted the first signal.
Claim 6
Dependent Claim
298 words
A sequence controller comprising: a program storage means for storing a sequence program; external signal input terminals divided into multiple blocks, at least one block being subdivided into multiple groups, each group consisting of multiple terminals; an arithmetic and logic operation means having a program counter for outputting a memory address signal in synchronism with a timing signal, the arithmetic and logic operation means being adapted to perform logic operation on two or more signals including the external signals taken in from the external signal input terminals, according to a sequence program which was read out from the program storage means according to the memory address signal; an output means for outputting a control signal according to the result of operation performed by the arithmetic and logic operation means; a specifying means for specifying some of the external signal input terminals as an interrupt signal input terminal; first signal generating means for outputting a first signal when a signal calling for an interrupt processing comes to a particular terminal in a group to which the interrupt signal input terminals belong; second signal generating means for outputting a second signal when one of the blocks outputs the first signal; a second signal transfer means for informing the arithmetic and logic operation means that the second signal has occurred in one of the blocks; and an access means by which the arithmetic and logic operation means when informed by the second signal transfer means of the occurrence of the second signal stops its logic operation required by the sequence program, accesses the second signal generating means successively and, when it finds the block that has produced the second signal, successively accesses the first signal generating means belonging to that block to identify the unit which has outputted the first signal.
Claim 7
Dependent Claim
30 words
A sequence controller as set forth in claim 4, wherein the specifying means specifies the external signal input terminals as an interrupt signal input terminal one group at a time.
Claim 8
Dependent Claim
33 words
A sequence controller as set forth in claim 4, wherein the specifying means specifies the external signal input terminals in the group as an interrupt signal input terminal one terminal at a time.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-03-12 | 1993-09-11 | 1994-03-13 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-03-12 | 1997-09-11 | 1998-03-13 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-03-12 | 2001-09-11 | 2002-03-13 | $7700.00 | Window Closed / Lapsed |