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US4908706A
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US
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Teletext decoder arrangements
Assignee: US Philips Corp
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Filing: 1989-02-14
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Granted: 1990-03-13
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Expires: 2009-02-14
Abstract
Abstract A teletext decoder arrangement has a page memory comprising a large number of chapters or portions in which individual pages can be stored. The arrangement has a plurality of data acquisition circuits which can acquire separate pages simultaneously. A register file is provided having a word location for each data acquisition circuit. A processor can load a memory chapter pointer byte into a word location when a page is to be acquired by the related data acquisition circuit so as to allot the memory chapter identified by the pointer byte for the storage of that page. In a practical embodiment four 4-bit word locations can have any one of 16 different 4-bit pointer bytes loaded into them to identify any one of 16 different memory chapters.
Inventors
- 👤 Richard E. F. Bugg
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 20:48
CPC Classifications
H; H04; H04N; H04N7/00; H04N7/08; H04N7/087; H04N7/088; H04N7/0882
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
190 words
A teletext decoder arrangement comprising a plurality of data acquisition circuits, a memory having a capacity for storing a large number of acquired pages in separate memory chapters, first addressing means for addressing the chapters individually and second addressing means for addressing byte locations in each chapter, which teletext decoder arrangement is characterised in that said first addressing means includes a register file having a number of word locations in each of which any one of a plurality of different pointer bytes can be stored, said word locations being addressable, to read out a pointer byte stored therein, by respective word addresses each of which pertains to a respective one of the data acquisition circuits, each of said pointer bytes identifying according to its bit values a respective memory chapter and each being usable when read out from a word location to select its memory chapter for the storage therein of a page acquired by the appertaining data acquisition circuit, the arrangement further including processor means for identifying the word location concerned by its word address and for determining the bit values of the pointer byte in that word location.
Claim 2
Dependent Claim
190 words
A teletext decoder arrangement comprising a plurality of data acquisition circuits, a memory having a capacity for storing a large number of acquired pages in separate memory chapters, first addressing means for addressing the chapters individually and second addressing means for addressing byte locations in each chapter, which teletext decoder arrangement is characterised in that said first addressing means includes a register file having a number of word locations in each of which any one of a plurality of different pointer bytes can be stored, said word locations being addressable, to read out a pointer byte stored therein, by respective word addresses each of which pertains to a respective one of the data acquisition circuits, each of said pointer bytes identifying according to its bit values a respective memory chapter and each being usable when read out from a word location to select its memory chapter for the storage therein of a page acquired by the appertaining data acquisition circuit, the arrangement further including processor means for identifying the word location concerned by its word address and for determining the bit values of the pointer byte in that word location.
Claim 3
Dependent Claim
32 words
A teletext decoder arrangement as claimed in claim 1, characterised in that the register file comprises four 4-bit word locations each for storing any one of sixteen different chapter memory pointer bytes.
Claim 4
Dependent Claim
36 words
A teletext decoder arrangement as claimed in claim 1, characterised in that the register file comprises four 8-bit word locations each for storing any one of two hundred and fifty six different chapter memory pointer bytes.
Claim 5
Dependent Claim
45 words
A teletext decoder arrangement as claimed in claim 1, 2, or 3, characterised in that said processor means is further operable to list in a table register the identity of used memory chapters together with the page numbers of acquired pages which are stored therein.
Claim 6
Dependent Claim
61 words
A teletext decoder arrangement as claimed in claim 4, characterised in that said processor means is operable to continuously update the table register when the arrangement is in use and the table register is interrogated by the processor means when a page request is made to determine whether the requested page has already acquired and stored in a particular memory chapter.
Claim 7
Dependent Claim
25 words
A teletext decoder arrangement as claimed in claim 4, characterised in that said table register is provided in at least one of the memory chapters.
Claim 8
Dependent Claim
49 words
A teletext decoder arrangement as claimed in claims 1, 2 or 3, characterised in that said processor means is operable when a page request is made to interrogate all of the memory chapters to ascertain whether the requested page has already been acquired and stored in one of them.
Claim 9
Dependent Claim
16 words
A television receiver including a teletext decoder arrangement as claimed in claim 1, 2, or 3.
Claim 10
Dependent Claim
25 words
A teletext decoder arrangement as claimed in claim 5, characterized in that said table register is provided in at least one of the memory chapters.
Claim 11
Dependent Claim
13 words
A television receiver including a teletext decoder arrangement as claimed in claim 4.
Claim 12
Dependent Claim
13 words
A television receiver including a teletext decoder arrangement as claimed in claim 5.
Claim 13
Dependent Claim
13 words
A television receiver including a teletext decoder arrangement as claimed in claim 6.
Claim 14
Dependent Claim
13 words
A television receiver including a teletext decoder arrangement as claimed in claim 7.
References Cited (Backward Citations)
US4679083A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-03-12 | 1993-09-11 | 1994-03-13 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-03-12 | 1997-09-11 | 1998-03-13 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-03-12 | 2001-09-11 | 2002-03-13 | $7700.00 | Window Closed / Lapsed |