System enabling high-speed convolution processing of image data

Claim 1

A system (1) enabling high-speed convolution processing of image data, comprising at least one arithmetical unit (2) comprising a number of interconnected processing cells (11, 11') with at least partially common inputs (50) and which perform one- or two-dimensional convolutions with separable variables, and memory means (3) for memorising at least said data to be subjected to such convolution processing; wherein said processing cells (11, 11') are substantially identical and each comprises a multiplier (12) which is supplied to an adder (13) which is also supplied with said data for processing and with the coefficients of said processing operation, and the result of which is supplied with the output of a foregoing cell (11, 11'); the output of said adder (13) being supplied to a memory register (15, 15') the output (49) of which constitutes the output of the cell; and wherein said arithmetical unit (2) comprises a number of said cells (11') each comprising a second number of memory means (14') for the coefficients of said processing operation and registers (15') for memorising the output of the respective adder (13), said memory means (14') and said registers (15' ) being enabled "in columns" at each processing step, and comprising a scanner (33) which selectively connects to the input of the adder (13) of the first cell (11') an external input (p) or the outputs of the registers (15') of the last downstream cell (11'), in such a manner as to enable repeat processing with a number of steps equal to said second number and wherein, at each step, there is carried over to said scanner (33) the output of the register (15') of the last cell (11') enabled in the foregoing step.

Claim 2

A system (1) enabling high-speed convolution processing of image data, comprising at least one arithmetical unit (2) comprising a number of interconnected processing cells (11, 11') with at least partially common inputs (50) and which perform one- or two-dimensional convolutions with separable variables, and memory means (3) for memorising at least said data to be subjected to such convolution processing; wherein said processing cells (11, 11') are substantially identical and each comprises a multiplier (12) which is supplied to an adder (13) which is also supplied with said data for processing and with the coefficients of said processing operation, and the result of which is supplied with the output of a foregoing cell (11, 11'); the output of said adder (13) being supplied to a memory register (15, 15') the output (49) of which constitutes the output of the cell; and wherein said arithmetical unit (2) comprises a number of said cells (11') each comprising a second number of memory means (14') for the coefficients of said processing operation and registers (15') for memorising the output of the respective adder (13), said memory means (14') and said registers (15' ) being enabled "in columns" at each processing step, and comprising a scanner (33) which selectively connects to the input of the adder (13) of the first cell (11') an external input (p) or the outputs of the registers (15') of the last downstream cell (11'), in such a manner as to enable repeat processing with a number of steps equal to said second number and wherein, at each step, there is carried over to said scanner (33) the output of the register (15') of the last cell (11') enabled in the foregoing step.