Digital phase locked loop circuit

Claim 2

A digital phase locked loop circuit comprising: sampling means for sampling a reproduced analog signal of a digital signal at a sampling frequency higher than a bit rate of a transmission channel; operation means for arithmetically operating, by using data at three or more successive sampling points, an average phase of a point where the reproduced signal crosses a reference level relative to a predetermined sampling point, during a period of a plurality of sampling intervals defined by said successive sampling points; and phase locked loop means for generating a signal whose phase is locked at the clock signal of the transmission channel by using the average phase output from said operation means.

Claim 3

The phase locked loop circuit according to claim 1, in which said operation means includes adding means for obtaining a first value by adding the sums of the absolute values of the data at the sampling points located at both ends of the sampling interval including the reference level cross point, and further obtaining a second value by adding the absolute values each at one of the sampling points at both ends of the sampling interval including the reference level cross point, over a time period consisting of the plurality of sampling intervals, and dividing means for obtaining a ratio of said first and second values.

Claim 4

The phase locked loop circuit according to claim 1, in which said operation means includes averaging means for obtaining a first value by averaging the sums of the absolute values of the data at the sampling points located at both ends of the sampling interval including the reference level cross point, and further obtaining a second value by averaging the absolute values each at one of the sampling points at both ends of the sampling interval including the reference level cross point, over a time period consisting of the plurality of sampling intervals, and dividing means for obtaining a ratio of said first and second values.

Claim 5

The phase locked loop circuit according to claim 1, in which said operation means includes a correcting means for correcting the operation result of the average phase for the sampling points relating to the reference level cross point for the successive sampling intervals.

Claim 6

The phase locked loop circuit according to claim 4, in which said correcting means includes a means for obtaining the position and the number of the sampling interval including the reference level cross point, and make the correction of the operation result of the average phase on the basis of the obtained position and number of the sampling interval including the reference level cross point.

Claim 7

The phase locked loop circuit according to claim 4, in which said correcting means includes a means for making the correction of the operation result on the basis of the values at the sampling point located at both sides of the sampling interval including the reference level cross point.

Claim 8

The phase locked loop circuit according to claim 4, in which said correcting means includes a means for obtaining the position and the number of the sampling interval including the reference level cross point, and make the correction of the operation result of the average phase on the basis of the obtained position and number of the sampling interval including the reference level cross point, and further the values at the sampling point located at both sides of the sampling interval including the reference level cross point.

Claim 9

A digital phase locked loop circuit comprising: sampling means for sampling a reproduced analog signal of a digital signal at a sampling frequency higher than the bit rate of a transmission channel; operation means for arithmetically operating, by using data at a plurality of successive sampling points, an average phase of a point where the reproduced signal crosses a reference level relative to a predetermined sampling point, for a time period defined by successive sampling points; phase locked loop means for generating a signal whose phase is locked at the clock signal of the transmission channel by using the average phase output from said operation means; phase error detecting means located outside a phase locked loop by said phase locked loop and for obtaining the low frequency components of the phase error on the basis of the operation result by said operation means; and error correction means for correcting the phase of an input signal to said phase locked loop means by using the low frequency component of phase error derived from said phase error correcting means.

Claim 10

A digital phase locked loop circuit comprising: sampling means for sampling a reproduced analog signal of a digital signal at a sampling frequency higher than the bit rate of a transmission channel; operation means for arithmetically operating, by using data at a plurality of successive sampling points, an average phase of a point where the reproduced signal crosses a reference level relative to a predetermined sampling point, for a time period defined by successive sampling points; phase locked loop means for generating a signal whose phase is locked at the clock signal of the transmission channel by using the average phase output from said operation means; phase error detecting means located outside a phase locked loop by said phase locked loop and for obtaining the low frequency components of the phase error on the basis of the operation result by said operation means; and error correction means for correcting the phase of an input signal to said phase locked loop means by using the low frequency component of phase error derived from said phase error correcting means.

Claim 11

The phase locked loop circuit according to claim 8, in which said phase error detecting means includes a low-pass filter means for picking up the low frequency component of the operation result by said operation means.

Claim 12

The phase locked loop circuit according to claim 8, in which said low-pass filter means includes a leak integrating means.

Claim 13

The phase locked loop circuit according to claim 8, in which said operation means uses three or more successive sampling points.

Claim 14

The phase locked loop circuit according to claim 11, in which said operation means includes adding means for obtaining a first value by adding the sums of the absolute values of the data at the sampling points located at both ends of the sampling interval including the reference level cross point, and further obtaining a second value by adding the absolute values each at one of the sampling points at both ends of the sampling interval including the reference level cross point, over a time period consisting of the plurality of sampling intervals, and dividing means for obtaining a ratio of said first and second values.

Claim 15

The phase locked loop circuit according to claim 11, in which said operation means includes averaging means for obtaining a first value by averaging the sum of the absolute values of the data at the sampling points located at both ends of the sampling interval including the reference level cross point, and further obtaining a second value by averaging the absolute values each at one of the sampling points at both ends of the sampling interval including the reference level cross point, over a time period consisting of the plurality of sampling intervals, and dividing means for obtaining a ratio of said first and second values.

Claim 16

The phase locked loop circuit according to claim 11, in which said operation means includes a correcting means for correcting the operation result of the average phase for the sampling points relating to the reference level cross point for the successive sampling intervals.

Claim 17

The phase locked loop circuit according to claim 14, in which said correcting means includes a means for obtaining the position and the number of the sampling interval including the reference level cross point, and make the correction of the operation result of the average phase on the basis of the obtained position and number of the sampling interval including the reference level cross point.

Claim 18

The phase locked loop circuit according to claim 14, in which said correcting means includes a means for making the correction of the operation result on the basis of the values at the sampling point located at both sides of the sampling interval including the reference level cross point.

Claim 19

The phase locked loop circuit according to claim 14, in which said correcting means includes a means for obtaining the position and the number of the sampling interval including the reference level cross point, and make the correction of the operation result of the average phase on the basis of the obtained position and number of the sampling interval including the reference level cross point, and further the values at the sampling point located at both sides of the sampling interval including the reference level cross point.

Claim 20

A digital phase locked loop circuit comprising: sampling means for sampling a reproduced analog signal of a digital signal at a sampling frequency higher than a bit rate of a transmission channel; first operation means for obtaining a phase difference between a point where the reproduced analog signal crosses a reference level and a predetermined sampling point, in an interval between two successive sampling points; second operation means for obtaining an average of the phase differences obtained by said first operation means; and phase lock loop means for generating a signal whose phase is locked at the clock signal of the transmission channel by using the average obtained by said second operating means.

Claim 21

A digital phase locked loop circuit comprising: sampling means for sampling a reproduced analog signal of a digital signal at a sampling frequency higher than a bit rate of a transmission channel; first operation means for obtaining a phase difference between a point where the reproduced analog signal crosses a reference level and a predetermined sampling point, in an interval between two successive sampling points; second operation means for obtaining an average of the phase differences obtained by said first operation means; and phase lock loop means for generating a signal whose phase is locked at the clock signal of the transmission channel by using the average obtained by said second operating means.

Claim 22

A digital phase locked loop circuit comprising: sampling means for sampling a reproduced analog signal of a digital signal at a sampling frequency higher than a bit rate of a transmission channel; operation means for obtaining a phase of a point where the reproduced signal crosses a reference level relative to a predetermined sampling point when the reproduced analog signal crosses the reference level at one point, and for obtaining an average phase of points where the reproduced analog signal crosses the reference level relative to each predetermined sampling point when the reproduced analog signal crosses the reference level at a plurality of points, said operation means obtaining the phase or average phase in an interval between successive three or more sampling points; and phase lock loop means for generating a signal whose phase is locked at the clock signal of the transmission channel by using data obtained by said operating means.

Claim 23

A digital phase locked loop circuit comprising: sampling means for sampling a reproduced analog signal of a digital signal at a sampling frequency higher than a bit rate of a transmission channel; operation means for obtaining a phase of a point where the reproduced signal crosses a reference level relative to a predetermined sampling point when the reproduced analog signal crosses the reference level at one point, and for obtaining an average phase of points where the reproduced analog signal crosses the reference level relative to each predetermined sampling point when the reproduced analog signal crosses the reference level at a plurality of points, said operation means obtaining the phase or average phase in an interval between successive three or more sampling points; and phase lock loop means for generating a signal whose phase is locked at the clock signal of the transmission channel by using data obtained by said operating means.