Inverse-T LDDFET with self-aligned silicide

Claim 1

A process for preparing a lightly-doped drain field effect transistor with self-aligned silicide which comprises: a. defining a gate pattern by means of a photoresist mask on the silicon nitride layer of a laminate comprising a semiconductor substrate having deposited thereon successively a gate oxide layer, a polysilicon layer, and said silicon nitride layer; b. removing completely the unmasked silicon nitride layer and partially removing the unmasked polysilicon layer by anisotropically etching said layers and then stripping the photoresist layer; c. ion-implanting the resultant structure to form lightly-doped source/drain regions under said partially-etched polysilicon layer; d. depositing a CVD SiO 2 layer followed by an anisotropic etching to form oxide sidewall spacers; e. anisotropically etching the unmasked polysilicon completely to form a polysilicon layer having a relatively thick central portion and a relatively thin peripheral step and to expose a portion of the gate oxide layer of said laminate; f. ion-implanting the resultant structure to form source/drain regions under said exposed portions of said gate oxide layer; g. removing the sidewall spacers; h. oxidizing completely the thin peripheral polysilicon step and the sidewalls of the polysilicon central portion; i. removing the silicon nitride layer so as to expose the top surface of the gate region; j. removing the silicon dioxide layer on the source/drain regions so as to form a structure having polysilicon dioxide spacers on the side walls of said gate and having exposed source/drain regions; and k. forming self-aligned silicide layers on the exposed source/drain regions and the exposed gate region.