Abstract A synchronous programmable binary counter has a parallel section and a serial section, with the length (in bits) of the serial section being the same as the modulus of the parallel section. The parallel section counts on system clocks and produces two outputs. A parallel terminal count output is produced each time the parallel section count reaches a programmed value. A frame output is generated every time the parallel section reaches its maximum count and starts counting again. The serial counter section decrements its programmed value by one each time it receives a frame signal from the parallel section. This subtraction is accomplished by a half-adder and associated borrow flip-flop. The borrow flip-flop is set by each arrival of the frame signal. Between frame signals, the decremented programmed value is circulated in a shift register as the serial subtraction process is performed. When the serial section completes its countdown, it detects the all zeros condition in its circulating shift register and sets a flip-flop indicating that it has reached its terminal count. The overall counter will complete its count and will generate a terminal count output when the parallel counter section reaches its next terminal count. The maximum count possible from this counter is S * 2 S+S, where S is the length of the serial section and the maximum count of the parallel section.
A synchronous two-stage serial/parallel counter circuit comprising: a parallel counter section for counting on system clocks and producing a parallel terminal count output and a frame output; a serial counter section for counting on the frame output of the parallel counter section and producing a serial terminal count output, the serial counter section having as many bits in its length as the maximum count capacity of the parallel counter section; and means for producing a terminal count signal upon the simultaneous occurrence of the parallel terminal count and the serial terminal count.
Claim 2
Dependent Claim
92 words
A synchronous two-stage serial/parallel counter circuit comprising: a parallel counter section for counting on system clocks and producing a parallel terminal count output and a frame output; a serial counter section for counting on the frame output of the parallel counter section and producing a serial terminal count output, the serial counter section having as many bits in its length as the maximum count capacity of the parallel counter section; and means for producing a terminal count signal upon the simultaneous occurrence of the parallel terminal count and the serial terminal count.
Claim 3
Dependent Claim
22 words
A synchronous two-stage serial/parallel counter circuit as recited in claim 1 further comprising means for initializing the parallel and serial counter sections.
Claim 4
Dependent Claim
82 words
A synchronous two-stage serial/parallel counter circuit as recited in claim 2 wherein the initializing means is a load signal that resets the parallel counter section to a known state and the serial counter section to a precount condition established by the state of a set of serial data signals, and wherein the parallel counter section further comprises programmable means for recognizing a particular count of the parallel counter section to generate the parallel terminal count output, thus making the counter circuit programmable.
Claim 5
Dependent Claim
22 words
A synchronous two-stage serial/parallel counter circuit as recited in claim 1 wherein the parallel counter section comprises a linear feedback shift register.
Claim 6
Dependent Claim
125 words
A synchronous two-stage serial/parallel counter circuit as recited in claim 1 wherein the serial counter section comprises: a shift register coupled in a circular fashion for receiving a programming value and circulating an intermediate data value completely once each full count of the parallel counter section, such full count of the parallel counter section defining a circulation interval; means for subtracting disposed to subtract a one from the contents of the shift register each time that the intermediate data value circulates in the shift register and a frame signal has been received from the parallel section during the most recent circulation interval; and means for detecting when the shift register contains all zeros and outputting a serial terminal count signal in response to such detection.
Claim 7
Dependent Claim
20 words
A synchronous two-stage serial/parallel counter circuit as recited in claim 3 wherein the load signal is the terminal count signal.