Functional cache memory chip architecture for improved cache access

Claim 2

A VLSI cache memory subsystem including, on-chip a single-port, late-select, cache array organized to be n-way set associative said chip including a plurality of functionally interrelated units on-chip with the cache array which comprise; (1) means for performing a normal CPU read access operation including means for accessing the chip in a fast, "late-select" mode, which is n-way set-associative, in effectively one memory cycle for a read operation to the CPU, (2) means for performing an internal late-write operation including means for allowing a CPU "write" to one of n accessed words in effectively one cycle, and (3) means for performing a cache reload operation including means for providing a highly parallel multi-word store-back and reload operation to and from main memory, to reduce the reload time for a store-in cache organization, said means for performing the reload operation additionally including means for performing a nearly transparent, multiple word reload and including a Cache-Reload Buffer, a Store-Back Buffer and a load-thru mechanism all included on the chip for reloading, said system further including two separate decoders integrated on the chip, one actuable for normal single word read/write cache access by the CPU and one actuable for parallel multi-word cache reload, and means to access date in the Cache Reload Buffer which has been transferred out of main memory to the chip but not yet reloaded into the cache array, said two decoders providing two different accessing modes required for CPU or main memory operations.

Claim 3

A late-select VLSI cache memory subsystem chip comprising an array having a single access port and a plurality of functionally related elements entirely mounted on-chip with said array and efficiently interconnected therewith to provide enhanced functionality and speed, said subsystem chip including; n separate set-associative memory segments in the on-chip cache array, first addressing/decoding means interfacing the array with the CPU, comprising means for accessing first, n single logical words, one from each associative set in the array and for accessing next a single logical word from a single associative set from said n words as pointed to by the overall cache address presented to the system, second addressing/decoding means interfacing with the main memory for accessing an entire data block from a single associative set in the array, means utilizing said first addressing means for a normal cache read/write access, and means utilizing said second addressing means for memory store-back and cache reload operations, means for performing a late-write operation which allows a word to be written into the array from the CPU at one of n accessed words within a single memory cycle, control means including first buffers for interfacing logical words to be accessed to/from the cache and from/to the CPU in a single array access cycle, and control means including second buffers for interfacing blocks to be accessed to/from main memory and from/to the cache for reading/writing multiple logical words of a single associative set's data block in a single array access cycle.

Claim 4

A late-select VLSI cache memory subsystem chip comprising an array having a single access port and a plurality of functionally related elements entirely mounted on-chip with said array and efficiently interconnected therewith to provide enhanced functionality and speed, said subsystem chip including; n separate set-associative memory segments in the on-chip cache array, first addressing/decoding means interfacing the array with the CPU, comprising means for accessing first, n single logical words, one from each associative set in the array and for accessing next a single logical word from a single associative set from said n words as pointed to by the overall cache address presented to the system, second addressing/decoding means interfacing with the main memory for accessing an entire data block from a single associative set in the array, means utilizing said first addressing means for a normal cache read/write access, and means utilizing said second addressing means for memory store-back and cache reload operations, means for performing a late-write operation which allows a word to be written into the array from the CPU at one of n accessed words within a single memory cycle, control means including first buffers for interfacing logical words to be accessed to/from the cache and from/to the CPU in a single array access cycle, and control means including second buffers for interfacing blocks to be accessed to/from main memory and from/to the cache for reading/writing multiple logical words of a single associative set's data block in a single array access cycle.

Claim 5

A VLSI cache memory subsystem chip as set forth in claim 2, said first and second addressing/decoding means including a common portion for selecting a particular row in said array, said row including a multiple word data block for each of the n associative sets in said array.

Claim 6

A VLSI cache memory subsystem chip as set forth in claim 3 including late-select means for providing a signal to said chip indicating which associative set is required for a particular access.

Claim 7

A VLSI cache memory subsystem chip as set forth in claim 4 including Store-Back Buffer means for temporarily storing a multiple-word data block accessed via said second addressing/decoding means and means for storing said data block in said Store-Back Buffer prior to transfer to the main memory, and means for accessing said Store-Back Buffer means to transfer a block of data to the main memory.

Claim 8

A VLSI cache memory subsystem chip as set forth in claim 5 including a Cache-Reload Buffer for storing a multi-word data block transferred from main memory for reloading into the cache array via said second addressing/decoding means, and internal bus means on said chip having a band width equal to the complete multi-word data block to be accessed in a single associative set within said array connected between the array, the Store-Back Buffer and the Cache-Reload Buffer.

Claim 9

A VLSI cache memory subsystem chip as set forth in claim 6 wherein said Cache-Reload Buffer includes control means including a reload address register and means for interrogating the contents of said register on every normal read/write cache access from the CPU to determine if a requested data word is currently stored in said Cache-Reload Buffer, and means for accessing the addressed word in the Cache-Reload Buffer for read/write operations between the CPU and the cache chip.

Claim 10

A VLSI cache memory subsystem chip as set forth in claim 7 including control means associated with both said Cache-Reload Buffer and said Store-Back Buffer to indicate when the Cache-Reload Buffer has been fully loaded from main memory and for indicating when the Store-Back Buffer has transferred its complete contents to main memory and wherein the memory/cache bus has a narrower band width than said internal cache chip bus.

Claim 11

A VLSI cache memory subsystem chip as set forth in claim 2 including a load-through means comprising a data path for transferring an addressed logical word directly from main memory to the CPU externally of said array during reload when said logical word is transferred from main memory to the chip.

Claim 12

A VLSI cache memory subsystem chip as set forth in claim 9 wherein said load-thru means include a load-thru buffer and means for storing a particular data word therein before transferring same to the CPU.

Claim 13

A VLSI cache memory subsystem chip as set forth in claim 4 wherein the late-select mechanism includes means for detecting a late-select timing signal to activate the late-select operating mode in the array and means for decoding the late-select signal to determine which associative set is to be selected for any CPU access, main memory reload or store-back access.

Claim 14

A VLSI cache memory subsystem chip as set forth in claim 8 wherein said internal chip bus has a band width equal to the band width of a complete data block stored in the array and wherein a complete data block may be accessed in a single cache memory cycle for reload and store-back operations.

Claim 15

A VLSI cache memory subsystem chip as set forth in claim 12 including; a plurality of separate external circuit connections mounted on the chip boundary for receiving/transmitting data addresses and control signals from an off-chip memory control unit to the functional units of the chip, including connections to: a CPU data bus, a main memory data bus, an address bus, a "read" signal, a "write" signal, a load SBB signal, an unload SBB signal, a load CRB signal, an unload CRB signal, a chip select signal, a memory data valid signal, and a reset RAR & WFR signal.

Claim 16

A VLSI cache memory subsystem chip as set forth in claim 12 further including means for allowing the CPU to access a "valid" word in the CRB at a first cache address concurrently with the array being unloaded from a second cache address into the SBB.

Claim 17

A late-select VLSI cache memory subsystem chip comprising an array having a single access port and a plurality of functionally related elements entirely mounted on-chip with said array and efficiently interconnected therewith to provide enhanced functionality and speed, said subsystem chip including; n separate set-associative memory segments in the on-chip cache array, first addressing/decoding means interfacing the array with the CPU, comprising means for accessing first, n single logical words, one from each associative set in the array and for accessing next, a single logical word from a single associative set from said n words as pointed to by the overall cache address presented to the system, second addressing/decoding means interfacing with the main memory for accessing an entire data block from a single associative set in the array, said first and second addressing/decoding means including a common portion for selecting a particular row in said array, said row including a multiple word data block for each of the n associative sets in said array, means utilizing said first addressing means for a normal cache read/write access, and means utilizing said second addressing means for highly parallel multi-word memory store-back and cache reload operations, means for performing a late-write operation which allows a word to be written into the array from the CPU at one of n accessed words within a single memory cycle, control means including first buffers for accumulating logical words to be accessed to/from the cache and from/to the CPU in a single array access cycle, and control means including second buffers for accumulating blocks to be accessed to/from main memory and from/to the cache for reading/writing multiple logical words of a single associative set's data block in a single array access cycle, a late-select mechanism including means for providing a signal to said chip indicating which associative set is required for a particular access.

Claim 18

A late-select VLSI cache memory subsystem chip comprising an array having a single access port and a plurality of functionally related elements entirely mounted on-chip with said array and efficiently interconnected therewith to provide enhanced functionality and speed, said subsystem chip including; n separate set-associative memory segments in the on-chip cache array, first addressing/decoding means interfacing the array with the CPU, comprising means for accessing first, n single logical words, one from each associative set in the array and for accessing next, a single logical word from a single associative set from said n words as pointed to by the overall cache address presented to the system, second addressing/decoding means interfacing with the main memory for accessing an entire data block from a single associative set in the array, said first and second addressing/decoding means including a common portion for selecting a particular row in said array, said row including a multiple word data block for each of the n associative sets in said array, means utilizing said first addressing means for a normal cache read/write access, and means utilizing said second addressing means for highly parallel multi-word memory store-back and cache reload operations, means for performing a late-write operation which allows a word to be written into the array from the CPU at one of n accessed words within a single memory cycle, control means including first buffers for accumulating logical words to be accessed to/from the cache and from/to the CPU in a single array access cycle, and control means including second buffers for accumulating blocks to be accessed to/from main memory and from/to the cache for reading/writing multiple logical words of a single associative set's data block in a single array access cycle, a late-select mechanism including means for providing a signal to said chip indicating which associative set is required for a particular access.

Claim 19

A VLSI cache memory subsystem chip as set forth in claim 15 wherein the reload data path includes a store-back buffer for temporarily storing a multiple word data block accessed via said second addressing/decoding means when it is determined that said data block has been altered, and means for storing said data block in said Store-Back Buffer prior to transfer to the main memory, and means for accessing said Store-Back Buffer means to transfer data to the main memory, a Cache-Reload Buffer for storing a multi-word data block transferred from main memory for loading into the cache array via said second addressing/decoding means, and internal bus means on said chip having a band width equal to a complete multi-word data block to be accessed in a single associative set within said array connected between the array, the Store-Back Buffer and the Cache-Reload Buffer, and control means associated with both said Cache-Reload Buffer and said Store-Back Buffer means to indicate when the Cache-Reload Buffer has been fully loaded from main memory and for indicating when the store-back buffer has transferred its complete contents to main memory and wherein the memory/cache bus has a narrower band width than said internal cache chip bus.

Claim 20

A VLSI cache memory subsystem chip as set forth in claim 16 and further including; load-thru means comprising a data path for transferring an addressed logical word directly from main memory to the CPU externally of said array after the complete data block including said logical word is transferred from main memory to the chip, said Cache-Reload Buffer includes control means including a reload address register and means for interrogating the contents of said register on every normal read/write cache access from the CPU to determine if a requested data word is currently stored in said Cache-Reload Buffer, and means for accessing the addressed word in the Cache-Reload Buffer for read/write operations between the CPU and the cache chip, and wherein the late-select mechanism includes means for detecting a late-select timing signal to activate the late-select operating mode in the array and means for decoding the late-select signal to determine which associative set is to be selected for any CPU access, main memory reload or store-back access.